CPU halt during flash erase

[telemedcar]

Hello,

I am wondering if I/O hardware interrupts get lost during the time when CPU is halted due to flash erase.

Can Nordic also confirm if BLE data transmission in impacted negatively when flash activities are running. ( I am using the library "fstorage")

Best regards,

[Susheel Nuguru]

When you are using fstorage, then it uses a separate timeslot assigned from the BLE softdevice which is BLE friendly to do the flash operation. In simple terms, fstorage calls have lower priority than the BLE activity and hence cannot break BLE operations.

[telemedcar]

Thanks. Do I/O hardware interrupts get lost during the time when CPU is halted due to flash erase ?

[Susheel Nuguru]

flash erase can take long time, if there are more than one interrupt from the same source, then it will be only pended once to ARM NVIC as pending is single buffered. So yes , they can be lost.

[telemedcar]

can using PPI help to prevent the case that signal transitions can be lost when CPU is halted ?

[Susheel Nuguru]

not sure what you mean here. PPI can only be used to communicate between two peripherals within the nRF chip. You could probably do a PPI->Timer counter increment task connection to count how many events happened when the CPU is halted. But this method is very tricky to implement because you should find a way to enable this setup just before CPU is halted and disable it immediately when CPU wakes up else you will get false number in the Timer counter. What is your use case?