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ADC input maximum voltage

I have a sensor which has output in the range of 0-5V. I want to connect it to an nrf51822 GPIO pin and to be able to read the value via it's 10 bit ADC. Is there any guide on how to select the voltage divider values, prescaler etc??

  • That won't fly, you cannot exeed VDD+0.3V on any GPIO input.

    And since you need a divider anyway you can now design it to fit your selected reference voltage.

    Not more help possible at this point- as the OP did not provide the needed infos (impedance, accuracy).

  • I am aware of that 5V would potentially harm the GPIO so that I asked for some guidance in order to avoid such a situation. What parameters are essential to calculate a circuit that will drive the sensor to the ADC?

  • You can find recommendations on how to design the voltage divider in the nRF51 reference manual, section 31.1.5, page 165. sections 31.1.4 Input voltage range and 31.1.6 Input impedance can also be of interest. You can find the nRF51 reference manual here. infocenter.nordicsemi.com/.../nRF51_RM_v3.0.1.pdf

  • @Jorn according to my calculations I should use R2 - 1kOhm, R1 - 7.3kOhm for the voltage divider. What is the formula to calculate the capacitance? Is there a schematic on how to connect the FET? When using these values should I adjust the prescaling of ADC as well??

  • Due to the length of my answer to the question in the comment I will add this as an answer rather than a comment.

    The product specification states the capacitor should be able to hold the previous value for 20 us @ 8-bit sampling, and 68 us @ 10 bit sampling. The resistors and the capacitor can be seen as a standard RC filter, and the same calculations you would use for one applies here, with R being a combination of R1, R2 and Rain. You can then calculate the capacitor charge and discharge times, as well as the filters cut-off frequency. You want as little attenuation as possible within the band you are sampling, while long enough discharge time to maintain the voltage level for sampling (trade off scenario).

    The following blog post describes how to measure battery voltage with the ADC using a divider, and has a link where the calculations made for the capacitor can be found. devzone.nordicsemi.com/.../

    The FET would be connected with its drain connected to the power supply and its source to the first terminal of R1. Its gate would be connected to a GPIO pin, which would be toggled to control the current flow through the divider. As stated in the specification, the capacitor C is not needed when using a FET.

    Adjustment of the prescaler alters Rain, and should be taken into consideration when designing the divider. The input impedances are listed in table 313, page 166 of the product specification. This is also mentioned in the comment section of the blog post linked above.

    Best regards

    Jørn Frøysa

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