According to Table 19 in the nRF24L01+ datasheet, writing to any of the 32 command registers is "Executable in power down or standby modes only". This caveat is also repeated in the docs at the start of section 8.3.2 SPI timing.
The Status register is one of these 32 registers. So in PRX mode (CE high), when responding to RX_DR IRQ the clearing of status bits RX_DR, MAX_RT and TX_DS would appear to need to be done with CE low, but this means briefly turning off the receiver, potentially losing a packet and incurring a 130uS settling delay.
Looking through examples in library code sprinkled around the net, I've yet to see any implementations where the receiver is switched to standby mode in order to clear down the IRQ bits in the status reg. Worse still, if I simply bracket my own SPI command W_REGISTER -> STATUS with CE=0, CE=1, my receiver stops working where otherwise everything seems fine.
I'm really just asking if I'm interpreting the datasheet correctly.
