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Freeze/Halt the SPI SCK line while still sending data on MOSI?

Bit of an odd question but Im dealing with a rather wonky SPI peripheral and its got me trying to sort some interesting questions due to its strange data protocol. Im using an NRF52 and on SDK12.2 with the soft device enabled.

The chip Im working with has a two wire serial interface, the usual SCK and DATA IN. The first issue is that the chip reads that data line on both the rising and falling edge of the clock. Im pretty sure this is quite odd and there does not seem to be any good way to ensure that the correct data would be on the data line using the nordic standard SPI config. After some head scratching and deciding I really didn’t want to bitbang this data I had the bright idea to use a D-type flip flop IC between the NRF and the peripheral to essentially divide the SCK clock by two while still sending data at the same speed from the NRF side. This means the NRF will have updated the data by the next rise or fall of the SCK as the peripheral sees it. Haven’t tested this as Im waiting on the flip flop from digikey but hoping it works.

Now the next problem. The peripheral wants me to send over four pulses on the DI line while holding SCK either high or low (it doesn’t care) in order to latch. Again, quite the odd protocol and now Im struggling to see if there is a clean way to disable the SPI SCK while sending some data via the SPI driver on the NRF52 and then later re-enabling the SCK line so I can send more data.

So far my work around is literally to uninit the spi, reinit with the SCK pin set as unused, send my data pulses to latch, uninit, re-init with SCK back on a pin to send the real data, rinse and repeat. Surprisingly this works, except for it causes havoc with a second SPI peripheral on the other SPI channel which is updating at the same time. It also just seems like a silly way to do things. Worst case I'll use another NRF pin to either bit bang over the latch pulses or to disable the clock, but Im hoping theres something in the SDK that would let me freeze the clock pin without killing the spi entirely.

Thanks!

  • You can actually just disconnect the SPI peripherial from the pins using PSEL.XXX registers, for example:

    NRF_SPI0->PSEL.SCK = SPI_PSEL_SCK_PSELSCK_Disconnected;
    

    This will restore basic GPIO function. Later just reconnect the pin by writing the correct number.

    You might have to bitbang MOSI, though - the SCK must be connected according to the manual for SPI to work correctly.

  • Interesting, Ill have to try this as it seems like exactly what I needed, thanks! On a side note when I would reinit the spi with no SCK I was able to correctly send my pulses on the data line without the clock toggling but I did notice what seemed like a much longer lag than expected between the NRF sending my single bytes. I wonder if the SPI has a time out when there is no SCK, so it may be true the SCK must be connected in order for SPI to work correctly, in my case no SCK just means a slower data transfer which is fine. We'll have to see what happens.

  • So this answer worked for me, I did encounter issues with moving the SCK to disconnected and in the end I just shifted it to an unused pin, sent my latch data and then shifted it back.

    NRF_SPI0->PSEL.SCK = 25;
    nrf_drv_spi_transfer(&spi, buff_latch2, 14, m_rx_buf, 0);
    NRF_SPI0->PSEL.SCK = 12;
    
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