Hi, I am wondering why, sometimes, I get an odd packet out of order on the receiver. It is very random, it can occur at anytime, though usually it takes a minute or two. Testing shows that it does not seem to be an SPI issue.
The packets are in the correct order for the great majority of the time, but for example sometimes packet 14 will appear where packet 12 is supposed to be, or packet 15 where 11 is supposed to be. Also very rarely the interchanged packet may have the 8th bit high.
I am sending in one direction only, 23 bytes and have set this on TX and RX. The TX is transmitting about every 2ms, and the RX is receiving about every 30ms. So the RX FIFO would be filling up and discarding packets, but that is not an issue for this application. TX and RX at 250kbps;
The process I am following is loading TX buffer, then CE high,15uS delay, CE low, then flushing TX FIFO before next load, pipe 0 only, not using auto acknowledgement, SPI at 2Mbps and I am certain it is not an SPI issue.
At the receiver i am checking for RX FIFO IRQ, putting receiver into standby (CE low), receiving the payload, clearing IRQ, flushing RX FIFO, then turning the receiver on again (CE high) .
regards Tim
