Hello! I try to use three modules with chip nRF24L01 to syncronize two slave devices by one master device without wires. Required accuracy is about 10 nanoseconds. My idea is to send packet by master module, receive it by slave modules with same adresses and use the signal fall on IRQ pin of each slave module as a syncronization signal.
One module is configured in TX mode and periodically (50ms) sends one short packet without using Auto Acknowledgement. To receive this packet, two other modules configured in RX mode with same adresses, and RX_DR generate interrupt on the IRQ pin.
To send packet by tramsmitting module, I put one byte payload in TX FIFO by SPI command W_TX_PAYLOAD, than send command REUSE_TX_PL, and periodically (50ms) do high pulse on the CE for more than 10µs. On receiving module I poll IRQ pin, and when it becomes low, I send SPI commands to read status register, reset RX_DR bit and read RX_FIFO. Packet settings are: 3 address bytes, 1 byte payload, 1 byte CRC, 2Mbps.
TROUBLE: signal fall on IRQ pin of nRF24L01 of each receiving modules occurs not at the same time. And this difference is not a constant. There is a jitter about one microsecond! If I set datarate to 1Mbps, jitter increases to 2us.
In datasheet I found a parameter TIRQ = 8.2ηs @ 1Mbps, TIRQ = 6.0ηs @ 2Mbps (Figure 13 and 14) and as I understood time on air is fixed too. So I can't understand what is the source of this jitter. Am I doing something wrong? Or it is just impossible to make what I want on this chip?