nRF24L01 IRQ pin jitter on two modules in RX mode

AndrewT gravatar image

asked 2017-07-17 11:54:23 +0200

updated 2017-07-18 13:21:32 +0200

Hello! I try to use three modules with chip nRF24L01 to syncronize two slave devices by one master device without wires. Required accuracy is about 10 nanoseconds. My idea is to send packet by master module, receive it by slave modules with same adresses and use the signal fall on IRQ pin of each slave module as a syncronization signal.

One module is configured in TX mode and periodically (50ms) sends one short packet without using Auto Acknowledgement. To receive this packet, two other modules configured in RX mode with same adresses, and RX_DR generate interrupt on the IRQ pin.

To send packet by tramsmitting module, I put one byte payload in TX FIFO by SPI command W_TX_PAYLOAD, than send command REUSE_TX_PL, and periodically (50ms) do high pulse on the CE for more than 10µs. On receiving module I poll IRQ pin, and when it becomes low, I send SPI commands to read status register, reset RX_DR bit and read RX_FIFO. Packet settings are: 3 address bytes, 1 byte payload, 1 byte CRC, 2Mbps.

TROUBLE: signal fall on IRQ pin of nRF24L01 of each receiving modules occurs not at the same time. And this difference is not a constant. There is a jitter about one microsecond! If I set datarate to 1Mbps, jitter increases to 2us.

In datasheet I found a parameter TIRQ = 8.2ηs @ 1Mbps, TIRQ = 6.0ηs @ 2Mbps (Figure 13 and 14) and as I understood time on air is fixed too. So I can't understand what is the source of this jitter. Am I doing something wrong? Or it is just impossible to make what I want on this chip?


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Best regards!

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Hi Andrew,

Could you upload the images directly on your question ? The website can't get through the firewall at Nordic. The video file you can upload to youtube maybe.

1us seems to be quite big jitter. Here we have an example of time synchronization, it's for the nRF52 but the radio pretty similar to L01+. the author achieve 60ns mean difference . This is when compare the TX and RX not between RXs.

Hung Bui ( 2017-07-18 13:01:22 +0200 )editconvert to answer

Sorry I forgot to attach the link to the example here it is:

From your video, it seems that the distribution of latency mostly at +-0.5us and around 0us. I don't have an explanation for now. I will try to check with my colleagues who have more experience with the legacy chip, unfortunately most of them are on vacation.

Hung Bui ( 2017-07-19 09:22:40 +0200 )editconvert to answer