MBR Vector Table

[Ck]

I never worked with Cortex M0 before so I wonder how it's possible to jump to correct IRQ handler when I have my own bootloader and application which are using e.g. UART IRQ both.

I understand that Cortex M0 has only fixed vector table at addr. 0x0000 where MBR resides. If I'll use UART IRQ handler in bootloader and also in app so how does MBR Vector Table jump to correct UART IRQ handler? IRQ handler implementation within MBR contains jump to user IRQ handler?

Should I write into some specific RAM addres some specific value which distinguish between app and bootloader? So MBR IRQ handler can provide jump into my IRQ handler with correct offset?

[Hung Bui]

Hi Ck,

The MBR goes with softdevice, so you have to also take into account the softdevice.

So basically how it work is

1. MBR forwards the whole vector table to bootloader first.

2. The bootloader checks if softdevice update is not in progress. If not it will tell the MBR to forward the vector table to Softdevice vectortable instead of the bootloader's

3. After that the bootloader request the softdevice to forward those interrupt that is not blocked by the softdevice to the bootloader, in this case, it's included the UART IRQ. (using sd_softdevice_vector_table_base_set())

4. When the bootloader finishes, it will tell the softdevice to forward all the non-blocked interrupts to the appliation instead of itself. And after that start the application. (again, using sd_softdevice_vector_table_base_set())

Please add in the comment if you have further questions.