For the nRF51822 how the IO are connected to the VDD pins

[Andre Pouliot]

I'm currently debugging a daughter card for the nRF8122 evaluation board but there's a higher voltage and current on that daughter card.

I want to know how the IO are connected since the I have started debugging it we had incident and we had to scrap 2 evaluation card. One was completely burnout and the other one only have a few pins that have failed.

Are the digital IO arranged as a few pins together with the over-voltage protection diode together or each pins has independent protection? Is there a voltage protection for the analog port and where is it connected? Directly to AVDD or no protection?

Kinds Regard

[Stian Røed Hafskjold]

What is the voltage on the other card? In the PS the absolute maximum rating for the I/O is VDD+0.3 = 3.9 V. If the voltage is above this, you will significantly reduce the lifetime of the chip.

[Andre Pouliot]

The voltage for the daughter card is around 7.4V. But proper care as been done to do the voltage translation and input protection against over-voltage.

But we are switching high current on the daughter card and it may have caused a voltage spike to occur. I'm still investigating how it could happen.

One of the ADC did enter in contact with the higher voltage because of the manipulation of a connector. We do take care to prevent such event from occurring in the future. But that did burnout the evaluation card completely, like there wasn't any protection present for the ADC.