maximum interrupt frequency? GPIO vs GPIOTE

[ujwal]

Hi folks,

What's the maximum interrupt frequency the nRF51822 can support? I am looking to do an interrupt burst of about 4000 interrupts at a rate 2MHZ or 4MHz. In the ISR, I just want to read 8 GPIO input lines simultaneously.

Is this possible? Would I be better served with raw GPIO vs GPIOTE? I am thinking the GPIOTE driver will add some overhead?

I will be using a s110 soft device, but i could turn that off during this phase if it helps.

Thoughts?

Thanks

-ujwal

[RK]

You're not going to get near that. 2MHz is 8 cycles (clock is 16MHz). The interrupt latency of the Cortex-M0 is 16 cycles, that's 16 to stack and start the handler, and 16 to return from it afterwards (ignoring tail chaining). So even if your ISR did nothing at all your maximum interrupt frequency is every 32 cycles (22 with tail chaining) so 1/2 MHz.

Even 'just reading 8 GPIO lines simultaneously' would require loading a register with the address, (2 cycles), loading the data (2 cycles) plus, if you wanted to store it, another 4 cycles plus probably another 6 to increment the store-to address and test if you're done. That's 14. You can't just be reading it, you must have something, however minor, to do with the data.

At 4MHz you have 4 cycles, which isn't enough time to do anything at all.

With a piece of hand-crafted assembler you might, just, be able to read your 8 GPIOs plus the clock line (the one I assume you're hoping to use as an interrupt), detect it going low-high and store the rest of the data at .. possibly 1MHz .. just.

And all this is entirely incompatible with any softdevice or any other thing going on on the chip at all.

[ujwal]

Thank you RK! This is the conclusion I was coming to as well. Looks like I will have to cut my sampling rate way down. Hopefully, my sensor can support that. Accepting this answer.

[ujwal]

So, the way I will try to approach this is by using only one single interrupt instead of the burst to trigger the whole read. I will rely on the nRF51 clock to time myself on when to read the GPIO lines. In the interrupt handler, I seem to be able to read the 8 GPIO lines (pins 8-15) into an array at max rate of about 1.25MHz.

[Sylvain]

Hi RK,

Actually, I would like to fire up an interrupt on the rising edge of an external signal at a frequency higher than 100 kHz. So to test my code, I fire up an interrupt on his rising edge and in the interrupt I toggle an output. But, It seems that the maximum frequency is limited to 40 kHz.

However, I use a nRF52840 with a Cortex-M4F, I'm seeing that the interrupt latency for the Cortex-M4F is :

"Interrupt latency on entry is 12 cycles, plus a possible additional 17 cycles for Cortex-M4 with Floating Point Unit (FPU) implemented, and the latency on exit is ten cycles, plus a possible additional 17 cycles for Cortex-M4 with FPU."

So in the worst case, I'm able to launch an interrupt every 64*10^6/56 = 1.14 MHz. Right ?

Do you have an idea why I'm blocked to 40 kHz ?

Sincerely,
Sylvain