How to accurately calculate the output pin impedance to accurately develop a matching circuit?

I am currently developing an RF system whereby I want to use the nRF24L01 transceiver, although I'm quite new to RF design and the various intricacies that come with it. I am aware most circuits tend to match towards 50 ohms, what a smiths chart and the basic theory, but the only thing stopping me from accurately designing this circuit is how to figure out the source impedance of the ANT pins primarily. I know an easy solution would be to use the example circuit but I want to know why the various inductor and capacitor values were chosen, how its configuration in relation to the source and load impedance affects impedance and such. The data sheet of this transceiver only mentions the load impedance for maximum power output of (15 + j88) ohms, but no mention of the source impedance for the necessary pin. I simply just need insight from someone more experienced than myself so I can gain a more profound understanding.

  • The nRF24L01 matching network have 4 main functions, which dictates the topology: 

    1. Balun, transform from the differential ANT interface to a single ended antenna interface. This is done by creating a phase shift across the shunt inductor between ANT1 and ANT2. There are additional parasitic elements on-chip, like bonding wires, capacitors, etc. 

    2. Impedance transformation from the impedance the PA want to "see" into the matching network to a 50 ohm interface for the antenna

    3. Harmonic filtering by acting as a low pass filter, with series L and shunt C

    4. Provide a DC path from the VDD_PA pin to both ANT pins to power the PA via the inductors between the ANT pins and VDD_PA. 

    The component values are chosen to give best performance in terms of good output power and low harmonics. RX LO rejection is also part if this.. 

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