Issues with power on reset in nRF52840 - the chip hangs


this is about power-on-reset failure.

We have a board that has nRF52840 on it.
It operates in high voltage mode. The battery is connected to VDDH and REGOUT0 is programmed to output 3.3 V.

Sometimes, but not always we face an issue, then when the battery is completely drained, the device won't start at all and the only way to recover it is to disconnect and connect the battery again.

When the device is in this bad state, I measured low state on the nRF reset pin (0.075 V).
The VDD output (REGOUT0) is strange - it is not 3.3 V as programmed, it is not 1.8 V (default value), but 2.3 V instead.

The VDDH supply is normally 4.8 V from the battery through the battery management chip that has a boost converter.

I did a test, when the battery is almost completely drained, and probed VDDH and VDD. When the battery dies, I can observe that the device is doing power on resets, and eventually powers off. The VDD and VDDH lines rise and fall as in the waveform below (yellow VDDH, green VDD)

At the very end, I can see that VDDH rises slowly. Below zoomed in waveform of the last PoR:

I think this slow rise is a concern, as I found in the datasheet the following statement:

Note: The on-chip power-on reset circuitry may not function properly for rise times longer than
the specified maximum. (tR_VDD Supply rise time (0 V to 1.7 V) 60 ms)

Does this rise time apply to VDD or VDDH voltage in high voltage mode?
Or I should only care about tR_VDDH Supply rise time (0 V to 3.7 V) 100 ms?
V_DDH is specifies as min. 2.5 V and typical 3.7. Rise time specification is about rising up to 3.7, not 2.5.

Another point:
Note: In High Voltage mode, the configured output voltage for REG0 (REGOUT0 on page 46) must
not be greater than REG0 input voltage minus the voltage drop in REG0 (VDDH - VVDDH-VDD).

Normally the battery VDDH supply is 4.8 V which covers the requirement above REG0 3.3 < 4.8 - 0.3.
But given this long rise time, there is a period within which the VDDH is between 2.5 V and 3.6, when it's rising what can be seen on in the scope screenshots.
Can it make the power-on-reset circuitry upset?

Is the description above explaining the problem with the bricked board?
Does it violate the SOC specs?
If that's the case, is there any software solution for that?

  • When anticipating startup operation from a battery almost completely drained without knowing whether a high-current charging source is connected to the battery it is normal practice to prevent operation of the peripherals, cpu core and external hardware circuits until sufficient battery capacity is available to run these items without a resultant voltage dip forcing a reset. How to know when this is the case? Typically use a vanishingly short bare-metal ADC channel or comparator channel to sample the supply voltage and turn on a known drain (the cpu core as default or even maybe something like 500uA or 1mA peripheral) and monitor the supply for a short interval to see the voltage decay rate. If significantly fast immediately shut down the cpu core (sleep) before further fall in voltage and eventual reset.

    Safer designs would use an external device to do this, but the cpu itself works fine as long as the awake time is very short - ie no initialisation of other stuff such as bootloaders or BLE..

  • Hello,

    Using ADC to measure battery voltage, and take appropriate step to enter sleep until battery is replaced/recharged seems to be the way to go here yes. 

    I think you already understand what the problem is, but just to confirm your assumption: The last power sequence on I see on your screenshot is outside the recommended operating conditions of max 100ms rise time on VDDH: 


  • Thanks for your replies. As I expected, the best way to avoid the issue is to make sure the power supply rise times are within the specs.