SPI optimization

[valdev]

Hello I want to optimize SPI com as fast I can do: First I am using the fast spi data rate by SPI_FREQUENCY_FREQUENCY_M8 variable and I want to reduce at first the timing between the falling Chip Select edge and my first clock tick, and of course reduce the timing between the last clock tick and the rising Chip Select rising edge ...how can I process? Thanks!

[ovrebekk]

Hi

The official driver is interrupt based, and this adds a bit of overhead to each byte transfer. I wrote a polling based driver a while back, and it will be significantly quicker when running at higher bitrates: spi_master_fast.zip

As mentioned above the SPI master is only ratified up to 4MHz, and the reason for this is that we can not guarantee that the fall/rise times of the GPIO's will be quick enough to support 8MHz operation under all circumstances. By using the SPI at 8MHz you risk getting a system that works fine on one board, but fails on another for instance.

Under testing I find the library to give you a bitrate of approximately 4.2Mbps at 8MHz, and 3.5Mbps at 4MHz, so you are not gaining a lot of speed by using the 8MHz mode either.

At 4MHz the driver runs at about 90% of the ideal bitrate, and at 2MHz or lower it runs at 100%.

Best regards
Torbjørn

[valdev]

Many thanks for your help!