nRF52 maximum throughput of EasyDMA on PWM device

[puz_md]

Hello,

I've been looking a bit into the nRF52 product specification and I was just wondering how powerful EasyDMA is under extreme conditions.

Let's assume the following scenario: All 12 PWM channels are in use, with a frequency of 1 MHz. The duty cycle shall be set every period, which would result in a bandwith usage of 1MHz * 12 channels * 2 Bytes = 24 MB/s.

• How many cycles does an EasyDMA operation take?
• Will EasyDMA access the memory with 32 bit width (and update two PWM COMPARE registers at the same time?
• If there is concurrent EasyDMA access, will there be interleaving? Or may one EasyDMA device be blocked by a device of higher priority (e.g. the radio)?
• How will excessive EasyDMA load affect the remaining system? Can I calculate the impact on system performance (application speed)? Might the reliability of Bluetooth communication be affected?

And one more question concerning the PWM specification: Are the COMPARE registers double-buffered (and updated at the beginning of a PWM period)? Or are the new values applied just at the time of loading (which means during a PWM period)? In other words, if 12 COMPARE registers have to be updated through EasyDMA, might it happen that the later channels might use outdated values and it might come to glitches when their COMPARE registers are updated later?

Thanks for your help.

[ovrebekk]

Hi

• You can run one EasyDMA transfer per 2 16MHz clock cycles (every 125ns) maximum for each block of the RAM. The nRF52832 has 8 RAM blocks, so in theory you could run 8 EasyDMA transfers per 125ns if each transfer goes to its own RAM block.

• Yes, the PWM updates 2 compare values at once to utilize the 32-bit capacity of the EasyDMA.

• Higher priority devices will delay lower priority devices, but unless the higher priority device accesses the RAM 100% of the time there will interleaving naturally.

• If you assign one of the 8 RAM blocks to PWM exclusively there will be no impact on the system. If you put everything on the same block then lower priority channels will be delayed when there is a lot of BLE activity. In your case this means the PWM update would be pulled out to give priority to the radio, encryption modules and CPU. If the PWM doesn't get the update in time it will just replay the previous duty cycle, so there are no glitches, just a delayed update.

• The PWM register are double buffered, yes. As soon as it has loaded the current duty cycle it will request the next value, to make sure you have the entire interval time (1us) to get the new data.

Best regards
Torbjørn

[puz_md]

Hi Torbjørn, thanks for this high quality info! This really helps a lot! Just one question: You mention one EasyDMA transfer per 2 16MHz clock cycles. Shouldn't it be per 2 64MHz cycles on the nRF52?

[Eric Stutzenberger]

The APB Bus on the nRF52 is running at 16 MHz. So, even though the CPU core is running at 64 MHz, the APB peripheral clocks are still limited to 16 MHz. Check out the nRF52 Performance information here: infocenter.nordicsemi.com/.../performance.html

[puz_md]

I just saw it in the block diagram.. thanks.

[ovrebekk]

As mentioned most of the peripherals are clocked at 16MHz, to reduce power consumption and to make the peripheral behavior aligned with the nRF51. The same goes for the peripheral bus.

Feel free to accept the answer if you are happy with it :)