NRF5340 SPIS is it possible to update tx data during a transceive operation based on received data?

[Anthony Ambuehl]

I'm working with Zephyr using NCS 2.3.0.  The boards include nrf5340 and nrf9160.  

Project lead has specified that the nrt5340 shall operate as a SPI slave to the nrf9160.  The communication protocol calls for validating the received data on the fly as its received.  The received data starts with a length field.  The design specifies that after the indicated length of data is transceived, the spi master will clock out an additional byte and the slave should send a value  indicating whether the data received was found to be valid... essentially an ACK/NACK based on the received data.  The goal is to operate the SPI bus at up to 1 MHz.

For the UARTE interface I see there is an RXDY event after each byte is received, which allows simple byte-by-byte operation. I don't see anything similar in the SPIS peripheral.

Is this design feasible using the SPIS peripheral without an RXRDY event? 

Is it possible to return control to the caller of spi_tranceive after each byte without losing any data in the overall SPI transmission?  Given the 1 microsecond clock time, it seems like a very tight timing constraint to initiate another spi_transceive before the next byte starts clocking out.

[Turbo J]

Read the SPIS chapter in the PS that describes how the SPI slave peripherial works. It is impossible for the CPU to change bytes in a running SPIS transaction, you can only change the next one.

Your protocol design won't work with an MCU as SPI slave. These need noteworthy processing time in order to decide if a packed was valid or not. 

This SPI slave protocol would require an asic or FPGA in order to meet the <1µs timing.