Software triggered interrupts in nRF Connect SDK on nRF5340

Hello everybody,

getting more and more familiar with interrupts at bare metal level, my zero latency high priority direct interrupt is running flawlessly by now.

This time I want to add a software triggered interrupt with a lower priority which does some background processing, and which is triggered from within my zero latency interrupt once in a while. I already know that I can manually set the "Interrupt Pending" bit for a certain IRQ vector, which should normally trigger execution of this interrupt once the priority settings allows for it.

My question is: Which IRQ vector can I use for this? How many interrupt vectors are implemented in the nRF5340 core? Does the core implement IRQ vectors that are not routed to a peripheral device?

The include file nrf5340_application.h defines all the interrupt vectors present in the nRF5340 application core. Although, there are some interrupt vectors missing / not defined. For example 2, 4, 6, 7, 18, 19, ..., 56, 58-67 and 69+. Can I just pick one of these undefined vectors and use it as my "software interrupt"? Which is the maximum IRQ vector that I can use?

My other solution would be to use the IRQ vector of a peripheral device that I don't use in in combination with an interrupt in my implementation. For instance, I use the PWM1 device for generating some PWM signals on the I/O pins, but don't use the interrupt. In this case, in my theory, I could just use:

NVIC_SetPendingIRQ(PWM1_IRQn);

To manually trigger the PWM1 interrupt.

Will this concept work reliably on the nRF5340? And once again, is it possible to use undefined IRQ numbers for this? I'm still not sure which is the cleanest way to implement this.

Best regards!

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  • Just use the EGU for a software TASKS_TRIGGER[] or PPI-hardware interrupt, works really well:

    7.11 EGU — Event generator unit
    Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware (by PPI). This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible.

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  • Just use the EGU for a software TASKS_TRIGGER[] or PPI-hardware interrupt, works really well:

    7.11 EGU — Event generator unit
    Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware (by PPI). This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible.

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