Share the same pins on TWIM0 & TWIM1

[KWolfe81]

I would like to set up TWI transactions to two peripherals triggered by a single PPI event.  Reading prior forum posts, it looks like this can only be done if the transactions to the two peripherals are identical (e.g. sending/receiving the same number of bytes to each peripheral)  However, this doesn't match my use case. 

I had an idea that if I could configure and queue a transaction to peripheral A with TWIM0 and then a transaction to peripheral B with TWIM1, I could then chain the two transactions together (using PPI).  This would require having TWI0 and TWI1 share pins.  In my testing, I can configure them in this fashion perfectly fine and have it work if and only if one TWI instance is enabled at any given time.  I suspect this isn't working because what I've effectively done is create a multi-master TWI bus.

Is there any way around this limitation?  I suspect not but figured I'd ask the community at large.  Thanks!

[Maria Gilje]

Hello,

I have been assigned this ticket, and I will get back to you soon. In the meantime, I appreciate if you can share more information on what your goal is with this.

It is helpful if you can share more details on what you want to achieve with this. I.e. what is your use case?

  Reading prior forum posts,

Please share which posts these are.

I encourage the community to share their insights on this!

Regards,

Maria

[KWolfe81]

Scenario: I have two peripheral devices on the same TWI bus.  Every 5 mSec, I would like to automatically read 5 bytes from register 0x00 on peripheral A, and 20 bytes from register 0x10 on peripheral B. All of this would happen using PPI and zero CPU cycles.

Here's the link to a prior forum post stating that this can be done if the transactions to both peripherals are identical.

[Maria Gilje]

Have you looked into setting up a TEP fork? From the PPI documentation for nRF52833:

Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].

Best regards,

Maria

[KWolfe81]

I can set up the ppi chain fine. The issue is that the twi transactions do not begin when both twi peripherals are enabled.  

[Maria Gilje]

Have you considered a sequential read? I.e. the 5ms timeout is the EEP event which starts the TEP read task for peripheral A, and the TWIM STOPPED event is the EEP to trigger the TEP for reading from peripheral B.

[KWolfe81]

Again, setting up the PPI, events, and tasks isn't the issue.  If I have both TWI peripherals using the same pins and both are enabled, the transactions do not begin properly. (no, I am not attempting to execute both transactions at the same time).

I am going to close the ticket and assume this isn't possible due to the master-mode issue outlined in the original post.