How does an EGU register get a value?

Question

I have been trying to decipher the NRF specification documents to simply understand how PPI, interrupts, Tasks, Events, and EGUs are supposed to work together. I am still confused. Searching the DevZone, I came up with this post which refers to this nordic example . In this code, we have a handler function which is supposed to do stuff when EVENTS_TRIGGER[x] register has a "true" value. 
 void SWI1_EGU1_IRQHandler(void)
{
 if (NRF_EGU1->EVENTS_TRIGGERED[0] != 0)
 {
 NRF_EGU1->EVENTS_TRIGGERED[0] = 0;
 NRF_GPIOTE->TASKS_CLR[PWM1_GPIOTE_CH] = 1; // Turn on LED2.
 }
 if (NRF_EGU1->EVENTS_TRIGGERED[1] != 0)
 {
 NRF_EGU1->EVENTS_TRIGGERED[1] = 0;
 NRF_GPIOTE->TASKS_SET[PWM1_GPIOTE_CH] = 1; // Turn off LED2.
 }
}

Could anyone tell how this EVENT_TRIGGERED[x] part of "NRF_EGU1" gets a value? What writes that value?

As already mentioned by other people, the NGU documentation is confusing and minimalistic; it does not clearly explain the read/write flow (e.g. what writes where and such information).

hmolesworth · Accepted Answer

I can give a guide following my own understanding, probably not following the documentation .. anyway Hardware Events can trigger other Hardware Events. Any Hardware Event can optionally be linked to an interrupt vector. A Hardware Event is not an interrupt; Hardware Events and interrupts are enabled differently, one does not infer the other. 
 Here is my example of using an EGU to move some data processing out of a critical timing interrupt into a less-critical timing EGU interrupt to avoid missing the other time-critical timer events. I put this first (not what you are seeking) as it shows the exact way the EGU Hardware Event with corresponding EQU interrupt is triggered, in this case by a software instruction (instigating the Hardware Task): 
 // Event Generator Unit (EGUn)
static NRF_EGU_Type* pNRF_EGU = NRF_EGU4;
#define SWI_EGU_IRQn SWI4_EGU4_IRQn

void SWI4_EGU4_IRQHandler(void)
{
 // Handle the character ready to process event
 if (pNRF_EGU->EVENTS_TRIGGERED[0])
 {
 // Clear the character ready to process event
 pNRF_EGU->EVENTS_TRIGGERED[0] = 0;
 // Slow stuff goes here moved from timer interupt
 }
}

void init(void)
{
 // EGU setup Clear the character ready to process event
 pNRF_EGU->EVENTS_TRIGGERED[0] = 0;
 pNRF_EGU->INTENSET = 1;
 // Set interrupt priority lower priority than timer and enable interrupt
 NVIC_SetPriority(SWI_EGU_IRQn, 6+1);
 NVIC_ClearPendingIRQ(SWI_EGU_IRQn);
 NVIC_EnableIRQ(SWI_EGU_IRQn);
}
// This IRQ handler will trigger 3 times every Rx character bit
void TIMER3_IRQHandler(void)
{
 .. snip other events
 if (pTimer->EVENTS_COMPARE[4] == 1)
 {
 pTimer->EVENTS_COMPARE[4] = 0;
 if (blahblah
 {
 // Trigger the character ready to process event by activating the lower-priority EGU interrupt
 pNRF_EGU->TASKS_TRIGGER[0] = 1;
 }
} 
 Example of using an EGU to process a Hardware Event directly (not via software instruction) by instigating an EGU Hardware Event (Task) from the timer (or other) Hardware Event. This EGU Hardware Event can optionally trigger the associated EGU software interrupt: 
 // Event Generator Unit (EGUn)
static NRF_EGU_Type* pNRF_EGU = NRF_EGU4;
#define SWI_EGU_IRQn SWI4_EGU4_IRQn

void SWI4_EGU4_IRQHandler(void)
{
 // Handle the character ready to process event
 if (pNRF_EGU->EVENTS_TRIGGERED[0])
 {
 // Clear the character ready to process event
 pNRF_EGU->EVENTS_TRIGGERED[0] = 0;
 // etc
 }
}

void init(void)
{
 // Configure PPI channel with connection between pTIMER->EVENTS_COMPARE[4] and pNRF_EGU->TASKS_TRIGGER[0]
 NRF_PPI->CH[PPI_CHANNEL].EEP = (uint32_t)&pTimer->EVENTS_COMPARE[4];
 NRF_PPI->CH[PPI_CHANNEL].TEP = (uint32_t)&pNRF_EGU->TASKS_TRIGGER[0];
 // EGU setup Clear the character ready to process event
 pNRF_EGU->EVENTS_TRIGGERED[0] = 0;
 pNRF_EGU->INTENSET = 1;
 // Set interrupt priority lower priority than timer and enable interrupt
 NVIC_SetPriority(SWI_EGU_IRQn, 6+1);
 NVIC_ClearPendingIRQ(SWI_EGU_IRQn);
 NVIC_EnableIRQ(SWI_EGU_IRQn);
} 
 Any Hardware Event can similarly be linked to an EGU Hardware Event (and thus an EGU software interrupt) by this PPI mechanism.

How does an EGU register get a value?

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