Guidelines for design to minimize ESD-caused resets of nRF51?

[ScottBBBB]

We're having difficulty preventing our nRF51822 from resetting when ESD events occur. These events are not directly on the nRF51's I/O pins, and we've tried things like grounding the SWDCLK and SWDIO lines, but to no avail. Compared to other MCUs, the part seems quite sensitive. Are there guidelines available which can help us benefit from the experiences of others in this area?

Thanks, Scott

[ovrebekk]

Hi

Most likely what is happening is that the nRF51822 is entering debug mode, as this only requires SWDIO to be pulled low while SWDCLK is pulled high, something that could happen if you are hit by an ESD pulse.

Some pointers to reduce the chance of this happening are:

1. Put a 1,5kOhm pull up on SWDIO, and/or a 1nF cap to ground.

2. Put a 1,5kOhm pull down on SWDCLK

3. Ensure the SWDIO/SWDCLK signals are as short as possible on your PCB. The longer they are the more susceptible they become to ESD. Rather than routing them to edge connectors on the PCB, consider using test points that you can place closer to the chip.

4. If possible, avoid exposing the PCB in the final product (by using a plastic casing for instance).

While it might not help you at the moment, the nRF52 chip has been designed to avoid this problem by requiring a more complicated start sequence to enter debug mode.

Best regards
Torbjørn

[ovrebekk]

Hi

If your part goes into normal operating mode then the ESD event has probably just caused a normal pin reset. A 0.2us pulse on SWDIO/RESET should be sufficient to reset the device.

It's hard to provide an exact limit on SWDCLK speed based on the pull strength, as this will change depending on what debugger you are using, how long the signals are, and so forth. I would expect 1MHz to work fine with 1,5kOhm pull ups/downs, but you will have to do some testing on your own to be sure.