REG0 power consumption

Hello Nordic,

today I'm curious about power management!

Background

We are in development of two products (let's say A & B) both featuring Minew MS88F3 module (based on nRF52840 IC) and with two different power management topologies.

Product A

  • USB and Li-Po battery (3.7V nominal) supply
  • High Voltage mode
    • REG0 as LDO.
    • REGOUT0 is set to 2.7V
    • REG1 as DC/DC
  • Schematic:
    • VDD: LDO output
    • VDDH: diode-ored with BAT and USB (VCCM on shematic)
    • VBUS: connected to USB plug

  

Product B

  • 2xAA bateries (3.0V max) supply
  • Normal Voltage mode (SB1 ON) or High Voltage mode (SB1 OFF)
  • REGOUT0 is set to 1.8V (when in High Voltage mode)
  • Schematic:
    • VDD: if SB1 ON, then shorted to VDDH,
    • VDDH: connected to 2xAA battery
    • VBUS: not connected

NOTICE: Product B is prepared for evaluation purposes, therefore it has SB1 jumper to easy change voltage modes! 

Platform description:

  • IC:               nRF52840
  • Module:       Minew MS88SF3
  • SDK:            nRF5_SDK_17.1.0_ddde560
  • Softdevice:  s140_nrf52_7.2.0 
  • IDE:             SEGGER Embedded Studio for ARM Release 7.10a Build 2022121504.52072
  • OS:              Windows 10

Observations/Measurements

Current consumption measurements were taken using Power Profiler Kit II, at 100ksamp/sec and 2 minute window. Current consumption was measured on five different B products in both (normal and high) voltage modes and at different power supply levels. In all cases device was in connection with central device. Measurements were taken in three different configurations:

  1. Normal voltage mode (SB1 ON), REG1 LDO
  2. High voltage mode (SB1 OFF), REG1 LDO, REG0 LDO
  3. Normal voltage mode (SB1 ON), REG1 DC/DC

In all three test cases there was the same software, regarding calling "sd_power_dcdc_mode_set( NRF_POWER_DCDC_ENABLE ); " in 3. test case. Purpose of that measurements was to compare the power consumptions in various power configurations.

Results are following with Iavg (average current in uA) and Imax (max. current in mA) within 2 min window:

Notice the current consumption increase when in High voltage mode at battery voltage of 2.5V (REGOUT0 is set to 1.8V). Current increase from 2.0V -> 2.5V was ~10x for all 5pcs! Same increase can be observed from 2.5V->3.0V!

On the other hand product A has in High Voltage mode current consumption around ~50uA, measured from 4.2V to 3.0V.

Questions:

  1. Why does the current consumption raise proportional to supplied voltage in test case 2.? 
  2. On product B, when enabled high voltage mode, current consumption increases by ~100uA, but not in the product A. What can be the reason for that? One should expect at least 100uA current consumption on product A as this was measured on product B. 
  3. Schematic difference between A & B is that A have a VBUS connected and B does not. Can this have any effect on increased current consumption on product B, when in High voltage mode?
  4. What amount of current consumption does REG0 consume by itself when operating in LDO and when in DC/DC mode?

Thank you!

BR, Žiga

Parents
  • Hi Žiga,

    My analysis of the issue is as follows:

    1. Product A has low current consumption in high voltage mode, while product B has high current consumption in high voltage mode
      1. This means that quiescent current in REG0 is most likely not the issue here
      2. This is also in line with what I would expect. You should not see that much higher current consumption by just enabling REG0
    2. VBUS is not connected on product B
      1. This should not have any impact on the current consumption. Actually connecting VBUS will add a few microamps, not the other way around.
    3. The current increases linearly with voltage on VDDH
      1. Means that we have a resistive load on VDDH. (delta I with 0.5V increase => 0.5V/100uA ~ 5kOhm)
    4. You do not see the increased current in normal voltage mode, but you see high current in high voltage mode
      1. The difference in these two modes would be the voltage difference between VDD and VDDH
      2. Since we are looking at a resistive load on VDDH, and the fact that you do not see the elevated current in normal voltage mode, my guess is that this resistive load is placed between VDD and VDDH
        1. GPIOs (and SWD, nRESET, etc) are powered from the VDD domain, not VDDH.
          1. Having a pullup to VDDH (VBAT, VBUS, etc), on one of the GPIOs will allow for current to flow between VDDH and VDD.
        2. Things to check:
          1. External pullups on GPIOs, including SWD and nRESET lines
          2. If the Vref on the SWD header is connected to VDDH, not VDD (relevant only when the debugger is connected)
          3. External components, and their GPIO voltages. If external components are powered by VDDH, they will have a different voltage level, and current will flow between the devices. Level shifters must be used.
          4. Without being able to look at your schematic it's difficult to pinpoint exactly where the current flows, but my guess is that the issue is something similar to the above suggestions. We can make the ticket private if that makes it easier for you to share the schematic.

    Best regards,
    Stian

Reply
  • Hi Žiga,

    My analysis of the issue is as follows:

    1. Product A has low current consumption in high voltage mode, while product B has high current consumption in high voltage mode
      1. This means that quiescent current in REG0 is most likely not the issue here
      2. This is also in line with what I would expect. You should not see that much higher current consumption by just enabling REG0
    2. VBUS is not connected on product B
      1. This should not have any impact on the current consumption. Actually connecting VBUS will add a few microamps, not the other way around.
    3. The current increases linearly with voltage on VDDH
      1. Means that we have a resistive load on VDDH. (delta I with 0.5V increase => 0.5V/100uA ~ 5kOhm)
    4. You do not see the increased current in normal voltage mode, but you see high current in high voltage mode
      1. The difference in these two modes would be the voltage difference between VDD and VDDH
      2. Since we are looking at a resistive load on VDDH, and the fact that you do not see the elevated current in normal voltage mode, my guess is that this resistive load is placed between VDD and VDDH
        1. GPIOs (and SWD, nRESET, etc) are powered from the VDD domain, not VDDH.
          1. Having a pullup to VDDH (VBAT, VBUS, etc), on one of the GPIOs will allow for current to flow between VDDH and VDD.
        2. Things to check:
          1. External pullups on GPIOs, including SWD and nRESET lines
          2. If the Vref on the SWD header is connected to VDDH, not VDD (relevant only when the debugger is connected)
          3. External components, and their GPIO voltages. If external components are powered by VDDH, they will have a different voltage level, and current will flow between the devices. Level shifters must be used.
          4. Without being able to look at your schematic it's difficult to pinpoint exactly where the current flows, but my guess is that the issue is something similar to the above suggestions. We can make the ticket private if that makes it easier for you to share the schematic.

    Best regards,
    Stian

Children
  •  you're absolutely right.

    As predicted, issue was:

    Means that we have a resistive load on VDDH. (delta I with 0.5V increase => 0.5V/100uA ~ 5kOhm)

    Pull-up gate resistor (470k) for P-ch MOSFET (act as a power switch for some measurement components) is placed between VDDH and uC pin (what is effectively VDD, when set to 1). Meaning that Ugs was -1.2V (when it should be 0V) what is enough for MOSFET to conduct and that was the source of unexpected current consumption, in High Voltage mode. In Normal Voltage mode there no such problem as VDDH=VDD and thus Ugs=0V, as it should be in idle mode.

    Thank you for you help!

    BR, Žiga

Related