Level based control of GPIOTE

Question

Hi,

I have a comparator acting as a UVLO, it connects to a NRF52 pin with a pull-up. The comparator also pulls down two other circuits using a diode, which in turn are connected to other NRF52 pins using pull-ups. It works well.

I'd like if possible to remove the diodes and connecting the UVLO signal via GPIO Event through PPI and controlling the other two pins via GPIOTE SET and CLEAR.

What I can't determine from the datasheet is whether once the initial output of GPIOTE is set if PPI & GPIOTE are fully async to the clock in which case it would be like level control where they couldn't miss an event, or whether the clock is working to determine the event (like a D gate) in which case potentially the event could be missed.

It is only a small optimisation but one I thought I'd look at as I was contemplating moving the comparator to the built-in one.

Andrew

hmolesworth · Accepted Answer

Pull-up and pull-down resistors can be enabled on an output pin on nRF52832 and nRF52840 (others not tested) and this is a really useful feature. 
 " A pull-resistor cannot be enabled on a output device " is not correct, although the Product Specification does show the pull-up and pull-down don't apply to an output pin. I have pointed out this issue in older posts, but the Product Specifications were not updated. 
 // Here are my measurement results, which prove the pullup/pull-down resistor is connected to the pin regardless
// of the input setting. nRF52832, 32MHz crystal, no 32kHz crystal, no Reset pin, SoftDevice loaded but not
// enabled, no peripherals enabled, idle. Power CR2032 coin cell, no ground other than PPK-2, no J-Link.
//
// This first table is default port settings after a reset, no changes:
//
// PPK-2 Meter Conditions
// ====== ====== ==========
// 1.66uA 2.971V with errata workarounds, no i/o
// 1.51uA 2.985V no errata workarounds, no i/o
//
// This Next table is port settings made after a reset, all 32 port pins identical, nothing connected to any of
// the 32 port pins, no errata applied:
//
// PPK-2 Meter Direction Input Pullup Drive Level Sense Level Output
// ====== ====== ========== ============== ============ ============== ============== ===========
//
// 1.49uA 2.989V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLNONE | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven Low
// 1.49uA 2.999V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLDOWN | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven Low
// 6.47mA 2.894V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLUP | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven Low
// 6.47mA 2.889V (PIN_OUTPUT | PIN_CONNECT | PIN_PULLUP | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven Low
//
// 1.51uA 2.959V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLNONE | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven High
// 6.42mA 2.877V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLDOWN | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven High
// 1.53uA 2.938V (PIN_OUTPUT | PIN_DISCONNECT | PIN_PULLUP | PIN_DRIVE_S0S1 | PIN_SENSE_OFF) Driven High
//
//
// This shows setting a port pin into active low output driven low is as good as leaving a pin floating
// when unused, with the added benefit that there is no possibility of port feedthrough if a floating pin
// drifts through the threshold.
//
// Looking at pull-up and pull down resistor values for the 32 pins:
//
// (2.877Volts / 6.42mA) * 32 ==> 14.34K Ohm
 
 Here is one of my older responses nrf52832-power-leakage which stian reported internally at the time

Level based control of GPIOTE

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