nPM1100-QDA Pinout Documentation Fixed?

[Colby]

After reviewing the various reference designs from the infocenter, download sections, and the datasheet, I believe the use of Pin 18 on the QFN package of the nPM1100-QDA has yet to be cleared up.

Referencing a past devzone post:  nPM1100 Datasheet Pin Out  It appears that this issue was previously brought up and that Pin 4 was also an issue. It looks like Pin 4 has now been updated in some of the reference designs as an "AVSS" pin, but Pin 18 is still shown to be connected to GND.

The v1.3 Product Specification looks to be the most out of date as the 8.1.2 QFN24 pin assignments still lists Pin 4 as NC.

At this point, I am having to mostly reference the reference design material provided in the download section of the product page, but I want to make sure about whether Pin 18 should be grounded or not, as the existing reference designs do not match the message from the linked devzone post which stated: "Pin 18 to be left unconnected, as it is NC. Schematics will be fixed"

[ketiljo]

Pin 18 is indeed NC, i.e not bonded or in use. The reason for it to be shown as GND is because of the layout. It improves the grounding if you can connect the center pad to the top layer ground plane via this pin: 

[Colby]

Howdy ketiljo,

Thank you for the response, that clears up why it is still shown as connected to GND in the reference designs...

Is there a reason that a via-in-pad or two can't be used on the thermal (center) pad in this case?

Are there any other design considerations for connecting or not connecting Pin 18 (and the other two NC pins)? I know on some RF designs it is recommended to GND NC pins on some devices so the amount of floating copper is decreased, not sure it makes a big difference here one way or the other, so grounding seems like the only consideration.

[ketiljo]

The center pad has vias as well, but they don't show properly in the screenshot. The center pad is the main ground connection. Pin 18 is just to improve the top layer ground. It looks like this in Altium Designer: