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Delay GPIOTE events (synchronize handling of external interrupts)

Good morning,

I am using nRF51 SDK v10.0.0 and I have to synchronize access to a hardware resource shared between two control flows. One flow is an interrupt handler invoked by GPIOTE (high accuracy, using the hardware registers). I can use nrf_drv_gpiote_in_event_enable() and nrf_drv_gpiote_in_event_disable() to enable or disable the interrupt handler.

My question is: Can I use these functions to delay the interrupt or will it be completely lost in this case? The GPIOTE driver documentation does not give any information about how to delay interrupts during critical sections.

Example:

  • nrf_drv_gpiote_in_init() is called
  • nrf_drv_gpiote_in_event_enable() is called
  • nrf_drv_gpiote_in_event_disable() called
  • interrupt is triggered on the disabled GPIOTE pin
  • nrf_drv_gpiote_in_event_enable() is called a bit later

Will the interrupt handler be invoked by GPIOTE in this scenario?

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  • After some research, I decided to use the CMSIS NVIC_Enable/DisableIRQ() functions or the SETENA/CLRENA registers to disable the GPIOTE interrupt during main() SPI access. According to the Cortex M0 processor manual: "If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority." This is exactly what I need.

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  • After some research, I decided to use the CMSIS NVIC_Enable/DisableIRQ() functions or the SETENA/CLRENA registers to disable the GPIOTE interrupt during main() SPI access. According to the Cortex M0 processor manual: "If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority." This is exactly what I need.

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