SPI receives FF each time (MISO in high impedance)

[Tania V]

Hi Nordic team, 

I'm using an accelerometer ( FXLS8964AF from NXP) and the evaluation board nrf9160dk as master but I can't communicate them.

My code: 

#include <zephyr/kernel.h> 
#include <zephyr/device.h> 
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>

#define MY_SPI_MASTER DT_NODELABEL(my_spi_master)

// SPI master functionality
const struct device* _gSpiDev = DEVICE_DT_GET(MY_SPI_MASTER);

struct spi_cs_control spim_cs = {
.gpio = SPI_CS_GPIOS_DT_SPEC_GET(DT_NODELABEL(reg_my_spi_master)),
.delay = 0,
};

static const struct spi_config _gSpiCfg = {
.operation = SPI_WORD_SET(8) |
SPI_TRANSFER_MSB |
SPI_MODE_CPOL |
SPI_MODE_CPHA |
SPI_OP_MODE_MASTER,
.frequency = 1000000,
.slave = 0,
.cs = &spim_cs,
};

int main(void)
{

while(1){

if (!device_is_ready(_gSpiDev)) {
while(1);
}

if(!device_is_ready(spim_cs.gpio.port)){
while(1);
}

int ret;
uint8_t txBuf[2] = {0x80 | 0x13, 0x00}; // Read who am i register
uint8_t rxBuf[2];

const struct spi_buf txSpiBuf = {
.buf = txBuf,
.len = sizeof(txBuf),
};

const struct spi_buf_set txSpiBufSet = {
.buffers = &txSpiBuf,
.count = 1,
};

struct spi_buf rxSpiBuf = {
.buf = rxBuf,
.len = sizeof(rxBuf),
};

const struct spi_buf_set rxSpiBufSet = {
.buffers = &rxSpiBuf,
.count = 1,
};

ret = spi_transceive(_gSpiDev, &_gSpiCfg, &txSpiBufSet,&rxSpiBufSet);
if (ret < 0) {
while(1);
return 0;
}

txBuf[0] = (0x00 | 0x13); //Write test
txBuf[1] = 0x00;

ret = spi_transceive(_gSpiDev, &_gSpiCfg, &txSpiBufSet,&rxSpiBufSet);
if (ret < 0) {
while(1);
return 0;
}

return 0;
}

Overlay file:

&pinctrl {

    spi_master_default: spi_master_default {

        group1 {

            psels = <NRF_PSEL(SPIM_SCK, 0, 13)>,

                    <NRF_PSEL(SPIM_MOSI, 0, 11)>,

                    <NRF_PSEL(SPIM_MISO, 0, 12)>;

                    bias-pull-up;

        };

    };

    spi_master_sleep: spi_master_sleep {

        group1 {

            psels = <NRF_PSEL(SPIM_SCK, 0, 13)>,

                    <NRF_PSEL(SPIM_MOSI, 0, 11)>,

                    <NRF_PSEL(SPIM_MISO, 0, 12)>;

        };

    };

};  

my_spi_master: &spi2 {

    compatible = "nordic,nrf-spim";

    status = "okay";

    pinctrl-0 = <&spi_master_default>;

    pinctrl-1 = <&spi_master_sleep>;

    pinctrl-names = "default", "sleep";

    cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;

    clock-frequency = <1000000>;

    reg_my_spi_master: spi-device@0 {

        reg = <0>;

    };

};

Do you have any idea how I can solve this issue?

Please find attached pictures for "writing" and "reading" modes.

writing

reading

Thank you in advance.

Best regards,

Tania

[hmolesworth]

This accelerometer is slightly unusual in that to read a single byte requires a 24-bit (3 byte) transaction as the 2nd byte is basically ignored and allows internal timing stuff, so increase the Rx buffer size from 2 bytes to 3 bytes and the "I am .." response will be in the 3rd byte.

"SPI read operations with 4-wire mode A register read operation is initiated by transmitting a 1 for the R/W bit. Then, the 7- bit register read address, A[6:0] is encoded in the first byte. Following this first byte, a second byte of 0s or 1s (don't care condition) transfers. After this transfer completes, the next 8 SCLK cycles (pulses 17 through 24) output the selected register content"

// Tx can stay unchanged, Rx has to be 3 bytes minimum
uint8_t rxBuf[2];
// to
uint8_t rxBuf[3];

[Tania V]

Hi hmolesworth,

I will try it.

Do you know how I can change POL and CPHA of the clk?

From the actual configuration to CPOL=0 and CPHA=0.

It shows in the config struct but can I change it?

static const struct spi_config _gSpiCfg = {
.operation = SPI_WORD_SET(8) |
SPI_TRANSFER_MSB |
SPI_MODE_CPOL |
SPI_MODE_CPHA |
SPI_OP_MODE_MASTER,
.frequency = 1000000,
.slave = 0,
.cs = &spim_cs,
};

Thank you for your support.

[hmolesworth]

I don't have those definitions to hand, but you want both bitfields to be 0 so just comment SPI_MODE_CPOL and SPI_MODE_CPHA out or delete them as follows:

static const struct spi_config _gSpiCfg = {
   .operation = SPI_WORD_SET(8) |
   SPI_TRANSFER_MSB |
   SPI_OP_MODE_MASTER,
   .frequency = 1000000,
   .slave = 0,
   .cs = &spim_cs,
};

[Tania V]

Hi hmolesworth,

I had this result.

 

Regards,

Tania

[hmolesworth]

Data on MOSI looks correct except there are 4 bytes not 3 (which doesn't matter). Is pin 9 INTF_SEL correct? It must be high (VDD) for SPI.

spi_config needs input from Nordic, assuming it's similar to their example code. It looks ok.