Build error: undefined reference to `__device_dts_ord_144'

sdk: 2.4.2

Controller: nrf5340

Hello,

I want to add the simultaneous update feature to our application.

This means that we want to transfer the app-core-image and the net core-image simultaneous

via BLE into the external flash memory of our product.

I found the follwing example:

samples_for_nrf_connect_sdk/bootloader_samples/nrf5340/mcuboot_smp_ble_simultaneous at main · hellesvik-nordic/samples_for_nrf_connect_sdk · GitHub

This example is quite good. I only want  to change to the flash memory. In this example the QSPI flash memory mx25r64 is used.

I want use the simple SPI (no QSPI) flash memory mx25l16 which ist connected to SPI2.

So I modified the following files:

  • app. overlay 
  • mcuboot.overlay
  • mcuboot.conf

app. overlay

/ {
	chosen {
		nordic,pm-ext-flash = &mx25l16;
	};
};

&qspi {
	status = "disabled";
};

&spi2 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	cs-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&spi2_default>;
	pinctrl-1 = <&spi2_sleep>;
	pinctrl-names = "default", "sleep";

	mx25l16: mx25l16test@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <8000000>;
		label = "MX25L16TEST";
		jedec-id = [c2 20 15];
		sfdp-bfp = [
			e5 20 81 ff  ff ff 3f 00  00 ff 00 ff  08 3b 00 ff
			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 10 d8
			00 ff 00 ff
		];
		size = <16777216>;
		has-dpd;
		t-enter-dpd = <10000>;
		t-exit-dpd = <8800>;
	};
};


&pinctrl {
	spi2_default: spi2_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 1, 12)>,
				<NRF_PSEL(SPIM_MISO, 1, 14)>,
				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
		};
	};

	spi2_sleep: spi2_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 1, 12)>,
				<NRF_PSEL(SPIM_MISO, 1, 14)>,
				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
			low-power-enable;
		};
	};
};
&spi4_default {
	group1 {
		psels = <NRF_PSEL(SPIM_SCK, 1, 8)>,
		  <NRF_PSEL(SPIM_MISO, 1, 10)>,
		  <NRF_PSEL(SPIM_MOSI, 1, 9)>;
	};
};

&spi4_sleep {
	group1 {
		psels = <NRF_PSEL(SPIM_SCK, 1, 8)>,
		  <NRF_PSEL(SPIM_MISO, 1, 10)>,
		  <NRF_PSEL(SPIM_MOSI, 1, 9)>;
	};
};

&spi4 {
	cs-gpios = <&gpio1 11 0>;
};

mcuboot.overlay

/ {
	chosen {
		nordic,pm-ext-flash = &mx25l16;
	};
};

&qspi {
	status = "disabled";
};

&spi2 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	cs-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&spi2_default>;
	pinctrl-1 = <&spi2_sleep>;
	pinctrl-names = "default", "sleep";

	mx25l16: mx25l16test@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <8000000>;
		label = "MX25L16TEST";
		jedec-id = [c2 20 15];
		sfdp-bfp = [
			e5 20 81 ff  ff ff 3f 00  00 ff 00 ff  08 3b 00 ff
			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 10 d8
			00 ff 00 ff
		];
		size = <16777216>;
		has-dpd;
		t-enter-dpd = <10000>;
		t-exit-dpd = <8800>;
	};
};

&spi4 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&spi4_default>;
	pinctrl-1 = <&spi4_sleep>;
	pinctrl-names = "default", "sleep";
};

&pinctrl {
	spi2_default: spi2_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 1, 12)>,
				<NRF_PSEL(SPIM_MISO, 1, 14)>,
				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
		};
	};

	spi2_sleep: spi2_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 1, 12)>,
				<NRF_PSEL(SPIM_MISO, 1, 14)>,
				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
			low-power-enable;
		};
	};
};

mcuboot.conf:

# Enable flash simulator
CONFIG_FLASH=y
CONFIG_FPROTECT=y
CONFIG_PCD_APP=y
CONFIG_FLASH_SIMULATOR=y
CONFIG_FLASH_SIMULATOR_DOUBLE_WRITES=y
CONFIG_FLASH_SIMULATOR_STATS=n


# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# GS CONFIG_NORDIC_QSPI_NOR=y
# GS CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
# GS CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE=16

CONFIG_NORDIC_QSPI_NOR=n 
CONFIG_SPI=y 
CONFIG_SPI_NOR=y 
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

CONFIG_MAIN_STACK_SIZE=10240
CONFIG_BOOT_MAX_IMG_SECTORS=256


CONFIG_NRF53_MULTI_IMAGE_UPDATE=y
CONFIG_UPDATEABLE_IMAGE_NUMBER=2

CONFIG_BOOT_UPGRADE_ONLY=y
CONFIG_BOOT_IMAGE_ACCESS_HOOK_NRF5340=y
CONFIG_BOOT_IMAGE_ACCESS_HOOKS=y

CONFIG_LOG=y
CONFIG_LOG_DEFAULT_LEVEL=4

CONFIG_FLASH=y
CONFIG_FPROTECT=y
CONFIG_PM=n

CONFIG_BOOT_ENCRYPT_EC256=n
CONFIG_BOOT_ENCRYPT_RSA=n
CONFIG_BOOT_ENCRYPT_X25519=n
CONFIG_BOOT_SWAP_SAVE_ENCTLV=n

CONFIG_BOOT_BOOTSTRAP=n

CONFIG_ASSERT=n
CONFIG_BOOT_BANNER=n
CONFIG_CONSOLE=y
CONFIG_CONSOLE_HANDLER=n
CONFIG_GPIO=n
CONFIG_I2C=n
CONFIG_SPI=n
CONFIG_KERNEL_MEM_POOL=n
CONFIG_MINIMAL_LIBC_CALLOC=n
CONFIG_MINIMAL_LIBC_MALLOC=n
CONFIG_MINIMAL_LIBC_REALLOCARRAY=n
CONFIG_NCS_SAMPLES_DEFAULTS=y
CONFIG_NO_RUNTIME_CHECKS=y
CONFIG_NRF_RTC_TIMER=y
CONFIG_PRINTK=y
CONFIG_REBOOT=y
CONFIG_RESET_ON_FATAL_ERROR=y
CONFIG_SECURE_BOOT_DEBUG=n
CONFIG_SERIAL=y
CONFIG_SIZE_OPTIMIZATIONS=y
CONFIG_UART_CONSOLE=y

After building the modified example I got the following errors:

* Executing task: nRF Connect: Build: mcuboot_smp_ble_simultaneous/build (active)

Building mcuboot_smp_ble_simultaneous
C:\WINDOWS\system32\cmd.exe /d /s /c "west build --build-dir c:/Projekte/mcuboot_smp_ble_simultaneous/build c:/Projekte/mcuboot_smp_ble_simultaneous"

[0/13] Performing build step for 'mcuboot_subimage'
[1/11] Linking C executable zephyr\zephyr_pre0.elf
FAILED: zephyr/zephyr_pre0.elf zephyr/zephyr_pre0.map
cmd.exe /C "cd . && C:\DevTools\ncs\toolchains\31f4403e35\opt\zephyr-sdk\arm-zephyr-eabi\bin\arm-zephyr-eabi-gcc.exe -gdwarf-4 zephyr/CMakeFiles/zephyr_pre0.dir/misc/empty_file.c.obj -o zephyr\zephyr_pre0.elf -fuse-ld=bfd -T zephyr/linker_zephyr_pre0.cmd -Wl,-Map=C:/Projekte/mcuboot_smp_ble_simultaneous/build/mcuboot/zephyr/zephyr_pre0.map -Wl,--whole-archive app/libapp.a zephyr/libzephyr.a zephyr/arch/common/libarch__common.a zephyr/arch/arch/arm/core/aarch32/libarch__arm__core__aarch32.a zephyr/arch/arch/arm/core/aarch32/cortex_m/libarch__arm__core__aarch32__cortex_m.a zephyr/arch/arch/arm/core/aarch32/cortex_m/cmse/libarch__arm__core__aarch32__cortex_m__cmse.a zephyr/arch/arch/arm/core/aarch32/mpu/libarch__arm__core__aarch32__mpu.a zephyr/lib/libc/minimal/liblib__libc__minimal.a zephyr/soc/arm/common/cortex_m/libsoc__arm__common__cortex_m.a zephyr/drivers/clock_control/libdrivers__clock_control.a zephyr/drivers/console/libdrivers__console.a zephyr/drivers/flash/libdrivers__flash.a zephyr/drivers/pinctrl/libdrivers__pinctrl.a zephyr/drivers/serial/libdrivers__serial.a zephyr/drivers/timer/libdrivers__timer.a modules/nrf/lib/fprotect/lib..__nrf__lib__fprotect.a modules/nrf/lib/fatal_error/lib..__nrf__lib__fatal_error.a modules/nrf/subsys/pcd/lib..__nrf__subsys__pcd.a modules/nrf/modules/mcuboot/hooks/lib..__nrf__modules__mcuboot__hooks.a modules/nrf/drivers/hw_cc310/lib..__nrf__drivers__hw_cc310.a modules/mcuboot/boot/bootutil/zephyr/libmcuboot_util.a modules/mbedtls/libmodules__mbedtls.a modules/hal_nordic/nrfx/libmodules__hal_nordic__nrfx.a -Wl,--no-whole-archive zephyr/kernel/libkernel.a zephyr/CMakeFiles/offsets.dir/./arch/arm/core/offsets/offsets.c.obj -L"c:/devtools/ncs/toolchains/31f4403e35/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/thumb/v8-m.main/nofp" -LC:/Projekte/mcuboot_smp_ble_simultaneous/build/mcuboot/zephyr -lgcc zephyr/arch/common/libisr_tables.a -mcpu=cortex-m33 -mthumb -mabi=aapcs -Wl,--gc-sections -Wl,--build-id=none -Wl,--sort-common=descending -Wl,--sort-section=alignment -Wl,-u,_OffsetAbsSyms -Wl,-u,_ConfigAbsSyms -nostdlib -static -Wl,-X -Wl,-N -Wl,--orphan-handling=warn -Wl,-no-pie C:/DevTools/ncs/v2.4.2/nrfxlib/crypto/nrf_cc312_platform/lib/cortex-m33/soft-float/no-interrupts/libnrf_cc312_platform_0.9.17.a && cmd.exe /C "cd /D C:\Projekte\mcuboot_smp_ble_simultaneous\build\mcuboot\zephyr && C:\DevTools\ncs\toolchains\31f4403e35\opt\bin\cmake.exe -E echo ""
c:/devtools/ncs/toolchains/31f4403e35/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd.exe: zephyr/drivers/flash/libdrivers__flash.a(spi_nor.c.obj):(.rodata.spi_nor_config_0+0x0): undefined reference to `__device_dts_ord_144'
c:/devtools/ncs/toolchains/31f4403e35/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd.exe: zephyr/drivers/flash/libdrivers__flash.a(spi_nor.c.obj):(.data.__compound_literal.0+0x0): undefined reference to `__device_dts_ord_30'
collect2.exe: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
FAILED: modules/mcuboot/mcuboot_subimage-prefix/src/mcuboot_subimage-stamp/mcuboot_subimage-build mcuboot/zephyr/zephyr.hex mcuboot/zephyr/zephyr.elf
cmd.exe /C "cd /D C:\Projekte\mcuboot_smp_ble_simultaneous\build\mcuboot && C:\DevTools\ncs\toolchains\31f4403e35\opt\bin\cmake.exe --build . --"
ninja: build stopped: subcommand failed.
FATAL ERROR: command exited with status 1: 'C:\DevTools\ncs\toolchains\31f4403e35\opt\bin\cmake.EXE' --build 'c:\Projekte\mcuboot_smp_ble_simultaneous\build'

* The terminal process terminated with exit code: 1.
* Terminal will be reused by tasks, press any key to close it.

I spent a lot of time to find the problem but without success.

How can I solve the problem ?

Best regards,

Georg 

Parents
  • Hi Georg

    Could you look look up in <build>/zephyr/zephyr.dts and check number 144 and number 30? 

    From your config I see that you have both CONFIG_SPI=y and further down CONFIG_SPI=n, so we should verify if the SPI is enabled or disabled

    Regards

    Runar

  • Hi Runar,

    thank you for your answer.

    I removed  "CONFIG_SPI=n" in mcuboot.conf, but this does not fix the error.

    I can't find  number 144 and 30 in the zephyr.dts .

    Do you mean the file: \build\zephyr\include\generated\devicetree_generated.h ?

    Here I can see 30->   *   30  /soc/peripheral@50000000/gpio@842800

    but the list ends with 143.

     zephyr.dts:

    /dts-v1/;
    
    / {
    	#address-cells = < 0x1 >;
    	#size-cells = < 0x1 >;
    	model = "Nordic NRF5340 DK NRF5340 Application";
    	compatible = "nordic,nrf5340-dk-nrf5340-cpuapp";
    	chosen {
    		zephyr,entropy = &cryptocell;
    		zephyr,flash-controller = &flash_controller;
    		zephyr,console = &uart0;
    		zephyr,shell-uart = &uart0;
    		zephyr,uart-mcumgr = &uart0;
    		zephyr,bt-mon-uart = &uart0;
    		zephyr,bt-c2h-uart = &uart0;
    		zephyr,bt-hci-rpmsg-ipc = &ipc0;
    		nordic,802154-spinel-ipc = &ipc0;
    		zephyr,ieee802154 = &ieee802154;
    		zephyr,ipc_shm = &sram0_shared;
    		zephyr,sram = &sram0_image;
    		zephyr,flash = &flash0;
    		zephyr,code-partition = &slot0_partition;
    		zephyr,sram-secure-partition = &sram0_s;
    		zephyr,sram-non-secure-partition = &sram0_ns;
    		nordic,pm-ext-flash = &mx25l16;
    	};
    	aliases {
    		led0 = &led0;
    		led1 = &led1;
    		led2 = &led2;
    		led3 = &led3;
    		pwm-led0 = &pwm_led0;
    		sw0 = &button0;
    		sw1 = &button1;
    		sw2 = &button2;
    		sw3 = &button3;
    		bootloader-led0 = &led0;
    		mcuboot-button0 = &button0;
    		mcuboot-led0 = &led0;
    		watchdog0 = &wdt0;
    		spi-flash0 = &mx25r64;
    	};
    	soc {
    		#address-cells = < 0x1 >;
    		#size-cells = < 0x1 >;
    		compatible = "nordic,nRF5340-CPUAPP-QKAA", "nordic,nRF5340-CPUAPP", "nordic,nRF53", "simple-bus";
    		interrupt-parent = < &nvic >;
    		ranges;
    		nvic: interrupt-controller@e000e100 {
    			#address-cells = < 0x1 >;
    			compatible = "arm,v8m-nvic";
    			reg = < 0xe000e100 0xc00 >;
    			interrupt-controller;
    			#interrupt-cells = < 0x2 >;
    			arm,num-irq-priority-bits = < 0x3 >;
    			phandle = < 0x1 >;
    		};
    		systick: timer@e000e010 {
    			compatible = "arm,armv8m-systick";
    			reg = < 0xe000e010 0x10 >;
    			status = "disabled";
    		};
    		ficr: ficr@ff0000 {
    			compatible = "nordic,nrf-ficr";
    			reg = < 0xff0000 0x1000 >;
    			status = "okay";
    		};
    		uicr: uicr@ff8000 {
    			compatible = "nordic,nrf-uicr";
    			reg = < 0xff8000 0x1000 >;
    			status = "okay";
    		};
    		sram0: memory@20000000 {
    			compatible = "mmio-sram";
    			reg = < 0x20000000 0x80000 >;
    		};
    		peripheral@50000000 {
    			#address-cells = < 0x1 >;
    			#size-cells = < 0x1 >;
    			ranges = < 0x0 0x50000000 0x10000000 >;
    			dcnf: dcnf@0 {
    				compatible = "nordic,nrf-dcnf";
    				reg = < 0x0 0x1000 >;
    				status = "okay";
    			};
    			oscillators: oscillator@4000 {
    				compatible = "nordic,nrf-oscillators";
    				reg = < 0x4000 0x1000 >;
    				status = "okay";
    			};
    			regulators: regulator@4000 {
    				compatible = "nordic,nrf-regulators";
    				reg = < 0x4000 0x1000 >;
    				status = "okay";
    			};
    			clock: clock@5000 {
    				compatible = "nordic,nrf-clock";
    				reg = < 0x5000 0x1000 >;
    				interrupts = < 0x5 0x1 >;
    				status = "okay";
    			};
    			power: power@5000 {
    				compatible = "nordic,nrf-power";
    				reg = < 0x5000 0x1000 >;
    				interrupts = < 0x5 0x1 >;
    				status = "okay";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x1 >;
    				gpregret1: gpregret1@551c {
    					compatible = "nordic,nrf-gpregret";
    					reg = < 0x551c 0x1 >;
    					status = "okay";
    				};
    				gpregret2: gpregret2@5520 {
    					compatible = "nordic,nrf-gpregret";
    					reg = < 0x5520 0x1 >;
    					status = "okay";
    				};
    			};
    			reset: reset-controller@5000 {
    				compatible = "nordic,nrf-reset";
    				reg = < 0x5000 0x1000 >;
    				status = "okay";
    			};
    			ctrlap: ctrlap@6000 {
    				compatible = "nordic,nrf-ctrlapperi";
    				reg = < 0x6000 0x1000 >;
    				status = "okay";
    			};
    			i2c0: i2c@8000 {
    				compatible = "nordic,nrf-twim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x8000 0x1000 >;
    				clock-frequency = < 0x186a0 >;
    				interrupts = < 0x8 0x1 >;
    				status = "disabled";
    			};
    			spi0: spi@8000 {
    				compatible = "nordic,nrf-spim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x8000 0x1000 >;
    				interrupts = < 0x8 0x1 >;
    				max-frequency = < 0x7a1200 >;
    				easydma-maxcnt-bits = < 0x10 >;
    				status = "disabled";
    			};
    			uart0: uart@8000 {
    				compatible = "nordic,nrf-uarte";
    				reg = < 0x8000 0x1000 >;
    				interrupts = < 0x8 0x1 >;
    				status = "okay";
    				current-speed = < 0x1c200 >;
    				pinctrl-0 = < &uart0_default >;
    				pinctrl-1 = < &uart0_sleep >;
    				pinctrl-names = "default", "sleep";
    			};
    			i2c1: arduino_i2c: i2c@9000 {
    				compatible = "nordic,nrf-twim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x9000 0x1000 >;
    				clock-frequency = < 0x61a80 >;
    				interrupts = < 0x9 0x1 >;
    				status = "okay";
    				pinctrl-0 = < &i2c1_default >;
    				pinctrl-1 = < &i2c1_sleep >;
    				pinctrl-names = "default", "sleep";
    				zephyr,concat-buf-size = < 0x100 >;
    				st25v: ST25V@1 {
    					compatible = "i2c-device";
    					reg = < 0x1 >;
    				};
    			};
    			spi1: spi@9000 {
    				compatible = "nordic,nrf-spim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x9000 0x1000 >;
    				interrupts = < 0x9 0x1 >;
    				max-frequency = < 0x7a1200 >;
    				easydma-maxcnt-bits = < 0x10 >;
    				status = "disabled";
    			};
    			uart1: arduino_serial: uart@9000 {
    				compatible = "nordic,nrf-uarte";
    				reg = < 0x9000 0x1000 >;
    				interrupts = < 0x9 0x1 >;
    				status = "disabled";
    				current-speed = < 0x1c200 >;
    				pinctrl-0 = < &uart1_default >;
    				pinctrl-1 = < &uart1_sleep >;
    				pinctrl-names = "default", "sleep";
    			};
    			spi4: arduino_spi: spi@a000 {
    				compatible = "nordic,nrf-spim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0xa000 0x1000 >;
    				interrupts = < 0xa 0x1 >;
    				max-frequency = < 0x1e84800 >;
    				easydma-maxcnt-bits = < 0x10 >;
    				rx-delay-supported;
    				rx-delay = < 0x2 >;
    				status = "okay";
    				cs-gpios = < &gpio1 0xb 0x1 >;
    				pinctrl-0 = < &spi4_default >;
    				pinctrl-1 = < &spi4_sleep >;
    				pinctrl-names = "default", "sleep";
    			};
    			i2c2: i2c@b000 {
    				compatible = "nordic,nrf-twim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0xb000 0x1000 >;
    				clock-frequency = < 0x186a0 >;
    				interrupts = < 0xb 0x1 >;
    				status = "disabled";
    			};
    			spi2: spi@b000 {
    				compatible = "nordic,nrf-spim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0xb000 0x1000 >;
    				interrupts = < 0xb 0x1 >;
    				max-frequency = < 0x7a1200 >;
    				easydma-maxcnt-bits = < 0x10 >;
    				status = "okay";
    				cs-gpios = < &gpio1 0xf 0x1 >;
    				pinctrl-0 = < &spi2_default >;
    				pinctrl-1 = < &spi2_sleep >;
    				pinctrl-names = "default", "sleep";
    				mx25l16: mx25l16test@0 {
    					compatible = "jedec,spi-nor";
    					reg = < 0x0 >;
    					spi-max-frequency = < 0x7a1200 >;
    					label = "MX25L16TEST";
    					jedec-id = [ C2 20 15 ];
    					sfdp-bfp = [ E5 20 81 FF FF FF 3F 00 00 FF 00 FF 08 3B 00 FF EE FF FF FF FF FF 00 FF FF FF 00 FF 0C 20 10 D8 00 FF 00 FF ];
    					size = < 0x1000000 >;
    					has-dpd;
    					t-enter-dpd = < 0x2710 >;
    					t-exit-dpd = < 0x2260 >;
    				};
    			};
    			uart2: uart@b000 {
    				compatible = "nordic,nrf-uarte";
    				reg = < 0xb000 0x1000 >;
    				interrupts = < 0xb 0x1 >;
    				status = "disabled";
    			};
    			i2c3: i2c@c000 {
    				compatible = "nordic,nrf-twim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0xc000 0x1000 >;
    				clock-frequency = < 0x186a0 >;
    				interrupts = < 0xc 0x1 >;
    				status = "disabled";
    			};
    			spi3: spi@c000 {
    				compatible = "nordic,nrf-spim";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0xc000 0x1000 >;
    				interrupts = < 0xc 0x1 >;
    				max-frequency = < 0x7a1200 >;
    				easydma-maxcnt-bits = < 0x10 >;
    				status = "disabled";
    			};
    			uart3: uart@c000 {
    				compatible = "nordic,nrf-uarte";
    				reg = < 0xc000 0x1000 >;
    				interrupts = < 0xc 0x1 >;
    				status = "disabled";
    			};
    			adc: adc@e000 {
    				compatible = "nordic,nrf-saadc";
    				reg = < 0xe000 0x1000 >;
    				interrupts = < 0xe 0x1 >;
    				status = "okay";
    				#io-channel-cells = < 0x1 >;
    				phandle = < 0x15 >;
    			};
    			timer0: timer@f000 {
    				compatible = "nordic,nrf-timer";
    				status = "disabled";
    				reg = < 0xf000 0x1000 >;
    				cc-num = < 0x6 >;
    				max-bit-width = < 0x20 >;
    				interrupts = < 0xf 0x1 >;
    				prescaler = < 0x0 >;
    			};
    			timer1: timer@10000 {
    				compatible = "nordic,nrf-timer";
    				status = "disabled";
    				reg = < 0x10000 0x1000 >;
    				cc-num = < 0x6 >;
    				max-bit-width = < 0x20 >;
    				interrupts = < 0x10 0x1 >;
    				prescaler = < 0x0 >;
    			};
    			timer2: timer@11000 {
    				compatible = "nordic,nrf-timer";
    				status = "disabled";
    				reg = < 0x11000 0x1000 >;
    				cc-num = < 0x6 >;
    				max-bit-width = < 0x20 >;
    				interrupts = < 0x11 0x1 >;
    				prescaler = < 0x0 >;
    			};
    			rtc0: rtc@14000 {
    				compatible = "nordic,nrf-rtc";
    				reg = < 0x14000 0x1000 >;
    				cc-num = < 0x4 >;
    				interrupts = < 0x14 0x1 >;
    				status = "disabled";
    				clock-frequency = < 0x8000 >;
    				prescaler = < 0x1 >;
    			};
    			rtc1: rtc@15000 {
    				compatible = "nordic,nrf-rtc";
    				reg = < 0x15000 0x1000 >;
    				cc-num = < 0x4 >;
    				interrupts = < 0x15 0x1 >;
    				status = "disabled";
    				clock-frequency = < 0x8000 >;
    				prescaler = < 0x1 >;
    			};
    			dppic: dppic@17000 {
    				compatible = "nordic,nrf-dppic";
    				reg = < 0x17000 0x1000 >;
    				status = "okay";
    			};
    			wdt: wdt0: watchdog@18000 {
    				compatible = "nordic,nrf-wdt";
    				reg = < 0x18000 0x1000 >;
    				interrupts = < 0x18 0x1 >;
    				status = "okay";
    			};
    			wdt1: watchdog@19000 {
    				compatible = "nordic,nrf-wdt";
    				reg = < 0x19000 0x1000 >;
    				interrupts = < 0x19 0x1 >;
    				status = "disabled";
    			};
    			comp: comparator@1a000 {
    				compatible = "nordic,nrf-comp";
    				reg = < 0x1a000 0x1000 >;
    				interrupts = < 0x1a 0x1 >;
    				status = "disabled";
    				#io-channel-cells = < 0x1 >;
    			};
    			egu0: egu@1b000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x1b000 0x1000 >;
    				interrupts = < 0x1b 0x1 >;
    				status = "okay";
    			};
    			egu1: egu@1c000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x1c000 0x1000 >;
    				interrupts = < 0x1c 0x1 >;
    				status = "okay";
    			};
    			egu2: egu@1d000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x1d000 0x1000 >;
    				interrupts = < 0x1d 0x1 >;
    				status = "okay";
    			};
    			egu3: egu@1e000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x1e000 0x1000 >;
    				interrupts = < 0x1e 0x1 >;
    				status = "okay";
    			};
    			egu4: egu@1f000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x1f000 0x1000 >;
    				interrupts = < 0x1f 0x1 >;
    				status = "okay";
    			};
    			egu5: egu@20000 {
    				compatible = "nordic,nrf-egu";
    				reg = < 0x20000 0x1000 >;
    				interrupts = < 0x20 0x1 >;
    				status = "okay";
    			};
    			pwm0: pwm@21000 {
    				compatible = "nordic,nrf-pwm";
    				reg = < 0x21000 0x1000 >;
    				interrupts = < 0x21 0x1 >;
    				status = "okay";
    				#pwm-cells = < 0x3 >;
    				pinctrl-0 = < &pwm0_default >;
    				pinctrl-1 = < &pwm0_sleep >;
    				pinctrl-names = "default", "sleep";
    				phandle = < 0x14 >;
    			};
    			pwm1: pwm@22000 {
    				compatible = "nordic,nrf-pwm";
    				reg = < 0x22000 0x1000 >;
    				interrupts = < 0x22 0x1 >;
    				status = "disabled";
    				#pwm-cells = < 0x3 >;
    			};
    			pwm2: pwm@23000 {
    				compatible = "nordic,nrf-pwm";
    				reg = < 0x23000 0x1000 >;
    				interrupts = < 0x23 0x1 >;
    				status = "disabled";
    				#pwm-cells = < 0x3 >;
    			};
    			pwm3: pwm@24000 {
    				compatible = "nordic,nrf-pwm";
    				reg = < 0x24000 0x1000 >;
    				interrupts = < 0x24 0x1 >;
    				status = "disabled";
    				#pwm-cells = < 0x3 >;
    			};
    			pdm0: pdm@26000 {
    				compatible = "nordic,nrf-pdm";
    				reg = < 0x26000 0x1000 >;
    				interrupts = < 0x26 0x1 >;
    				status = "disabled";
    			};
    			i2s0: i2s@28000 {
    				compatible = "nordic,nrf-i2s";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x28000 0x1000 >;
    				interrupts = < 0x28 0x1 >;
    				status = "disabled";
    			};
    			mbox: ipc: mbox@2a000 {
    				compatible = "nordic,mbox-nrf-ipc", "nordic,nrf-ipc";
    				reg = < 0x2a000 0x1000 >;
    				tx-mask = < 0xffff >;
    				rx-mask = < 0xffff >;
    				interrupts = < 0x2a 0x1 >;
    				#mbox-cells = < 0x1 >;
    				status = "okay";
    				phandle = < 0x12 >;
    			};
    			qspi: qspi@2b000 {
    				compatible = "nordic,nrf-qspi";
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x0 >;
    				reg = < 0x2b000 0x1000 >, < 0x10000000 0x10000000 >;
    				reg-names = "qspi", "qspi_mm";
    				interrupts = < 0x2b 0x1 >;
    				status = "disabled";
    				pinctrl-0 = < &qspi_default >;
    				pinctrl-1 = < &qspi_sleep >;
    				pinctrl-names = "default", "sleep";
    				mx25r64: mx25r6435f@0 {
    					compatible = "nordic,qspi-nor";
    					reg = < 0x0 >;
    					writeoc = "pp4io";
    					readoc = "read4io";
    					sck-frequency = < 0x7a1200 >;
    					jedec-id = [ C2 28 17 ];
    					sfdp-bfp = [ E5 20 F1 FF FF FF FF 03 44 EB 08 6B 08 3B 04 BB EE FF FF FF FF FF 00 FF FF FF 00 FF 0C 20 0F 52 10 D8 00 FF 23 72 F5 00 82 ED 04 CC 44 83 68 44 30 B0 30 B0 F7 C4 D5 5C 00 BE 29 FF F0 D0 FF FF ];
    					size = < 0x4000000 >;
    					has-dpd;
    					t-enter-dpd = < 0x2710 >;
    					t-exit-dpd = < 0x88b8 >;
    				};
    			};
    			nfct: nfct@2d000 {
    				compatible = "nordic,nrf-nfct";
    				reg = < 0x2d000 0x1000 >;
    				interrupts = < 0x2d 0x1 >;
    				status = "okay";
    			};
    			mutex: mutex@30000 {
    				compatible = "nordic,nrf-mutex";
    				reg = < 0x30000 0x1000 >;
    				status = "okay";
    			};
    			qdec0: qdec@33000 {
    				compatible = "nordic,nrf-qdec";
    				reg = < 0x33000 0x1000 >;
    				interrupts = < 0x33 0x1 >;
    				status = "disabled";
    			};
    			qdec1: qdec@34000 {
    				compatible = "nordic,nrf-qdec";
    				reg = < 0x34000 0x1000 >;
    				interrupts = < 0x34 0x1 >;
    				status = "disabled";
    			};
    			usbd: zephyr_udc0: usbd@36000 {
    				compatible = "nordic,nrf-usbd";
    				reg = < 0x36000 0x1000 >;
    				interrupts = < 0x36 0x1 >;
    				num-bidir-endpoints = < 0x1 >;
    				num-in-endpoints = < 0x7 >;
    				num-out-endpoints = < 0x7 >;
    				num-isoin-endpoints = < 0x1 >;
    				num-isoout-endpoints = < 0x1 >;
    				status = "okay";
    			};
    			usbreg: regulator@37000 {
    				compatible = "nordic,nrf-usbreg";
    				reg = < 0x37000 0x1000 >;
    				interrupts = < 0x37 0x1 >;
    				status = "okay";
    			};
    			flash_controller: flash-controller@39000 {
    				compatible = "nordic,nrf53-flash-controller";
    				reg = < 0x39000 0x1000 >;
    				partial-erase;
    				#address-cells = < 0x1 >;
    				#size-cells = < 0x1 >;
    				flash0: flash@0 {
    					compatible = "soc-nv-flash";
    					erase-block-size = < 0x1000 >;
    					write-block-size = < 0x4 >;
    					reg = < 0x0 0x100000 >;
    					partitions {
    						compatible = "fixed-partitions";
    						#address-cells = < 0x1 >;
    						#size-cells = < 0x1 >;
    						boot_partition: partition@0 {
    							label = "mcuboot";
    							reg = < 0x0 0x10000 >;
    						};
    						slot0_partition: partition@10000 {
    							label = "image-0";
    							reg = < 0x10000 0x40000 >;
    						};
    						slot0_ns_partition: partition@50000 {
    							label = "image-0-nonsecure";
    							reg = < 0x50000 0x30000 >;
    						};
    						slot1_partition: partition@80000 {
    							label = "image-1";
    							reg = < 0x80000 0x40000 >;
    						};
    						slot1_ns_partition: partition@c0000 {
    							label = "image-1-nonsecure";
    							reg = < 0xc0000 0x30000 >;
    						};
    						storage_partition: partition@f8000 {
    							label = "storage";
    							reg = < 0xf8000 0x8000 >;
    						};
    					};
    				};
    			};
    			kmu: kmu@39000 {
    				compatible = "nordic,nrf-kmu";
    				reg = < 0x39000 0x1000 >;
    				interrupts = < 0x39 0x1 >;
    				status = "okay";
    			};
    			vmc: vmc@81000 {
    				compatible = "nordic,nrf-vmc";
    				reg = < 0x81000 0x1000 >;
    				status = "okay";
    			};
    			gpio0: gpio@842500 {
    				compatible = "nordic,nrf-gpio";
    				gpio-controller;
    				reg = < 0x842500 0x300 >;
    				#gpio-cells = < 0x2 >;
    				status = "okay";
    				port = < 0x0 >;
    				phandle = < 0x13 >;
    			};
    			gpio1: gpio@842800 {
    				compatible = "nordic,nrf-gpio";
    				gpio-controller;
    				reg = < 0x842800 0x300 >;
    				#gpio-cells = < 0x2 >;
    				ngpios = < 0x10 >;
    				status = "okay";
    				port = < 0x1 >;
    				phandle = < 0x8 >;
    			};
    			ieee802154: ieee802154 {
    				compatible = "nordic,nrf-ieee802154";
    				status = "okay";
    			};
    		};
    		spu: spu@50003000 {
    			compatible = "nordic,nrf-spu";
    			reg = < 0x50003000 0x1000 >;
    			interrupts = < 0x3 0x1 >;
    			status = "okay";
    		};
    		gpiote: gpiote0: gpiote@5000d000 {
    			compatible = "nordic,nrf-gpiote";
    			reg = < 0x5000d000 0x1000 >;
    			interrupts = < 0xd 0x5 >;
    			status = "okay";
    		};
    		cryptocell: crypto@50844000 {
    			compatible = "nordic,nrf-cc312";
    			reg = < 0x50844000 0x1000 >;
    			status = "okay";
    			#address-cells = < 0x1 >;
    			#size-cells = < 0x1 >;
    			cryptocell312: crypto@50845000 {
    				compatible = "arm,cryptocell-312";
    				reg = < 0x50845000 0x1000 >;
    				interrupts = < 0x44 0x1 >;
    			};
    		};
    		gpiote1: gpiote@4002f000 {
    			compatible = "nordic,nrf-gpiote";
    			reg = < 0x4002f000 0x1000 >;
    			interrupts = < 0x2f 0x5 >;
    			status = "disabled";
    		};
    	};
    	pinctrl: pin-controller {
    		compatible = "nordic,nrf-pinctrl";
    		i2c1_default: i2c1_default {
    			phandle = < 0x4 >;
    			group1 {
    				psels = < 0xc0005 >, < 0xb0004 >;
    				nordic,drive-mode = < 0x6 >;
    			};
    		};
    		i2c1_sleep: i2c1_sleep {
    			phandle = < 0x5 >;
    			group1 {
    				psels = < 0xc0005 >, < 0xb0004 >;
    				low-power-enable;
    			};
    		};
    		uart0_default: uart0_default {
    			phandle = < 0x2 >;
    			group1 {
    				psels = < 0x14 >, < 0x20013 >;
    			};
    			group2 {
    				psels = < 0x10016 >, < 0x30015 >;
    				bias-pull-up;
    			};
    		};
    		uart0_sleep: uart0_sleep {
    			phandle = < 0x3 >;
    			group1 {
    				psels = < 0x14 >, < 0x10016 >, < 0x20013 >, < 0x30015 >;
    				low-power-enable;
    			};
    		};
    		pwm0_default: pwm0_default {
    			phandle = < 0xd >;
    			group1 {
    				psels = < 0x16001c >;
    			};
    		};
    		pwm0_sleep: pwm0_sleep {
    			phandle = < 0xe >;
    			group1 {
    				psels = < 0x16001c >;
    				low-power-enable;
    			};
    		};
    		qspi_default: qspi_default {
    			phandle = < 0xf >;
    			group1 {
    				psels = < 0x1d0011 >, < 0x1f000d >, < 0x20000e >, < 0x21000f >, < 0x220010 >, < 0x1e0012 >;
    				nordic,drive-mode = < 0x3 >;
    			};
    		};
    		qspi_sleep: qspi_sleep {
    			phandle = < 0x10 >;
    			group1 {
    				psels = < 0x1d0011 >, < 0x1f000d >, < 0x20000e >, < 0x21000f >, < 0x220010 >;
    				low-power-enable;
    			};
    			group2 {
    				psels = < 0x1e0012 >;
    				low-power-enable;
    				bias-pull-up;
    			};
    		};
    		uart1_default: uart1_default {
    			phandle = < 0x6 >;
    			group1 {
    				psels = < 0x21 >;
    			};
    			group2 {
    				psels = < 0x10020 >;
    				bias-pull-up;
    			};
    		};
    		uart1_sleep: uart1_sleep {
    			phandle = < 0x7 >;
    			group1 {
    				psels = < 0x21 >, < 0x10020 >;
    				low-power-enable;
    			};
    		};
    		spi4_default: spi4_default {
    			phandle = < 0x9 >;
    			group1 {
    				psels = < 0x40028 >, < 0x6002a >, < 0x50029 >;
    			};
    		};
    		spi4_sleep: spi4_sleep {
    			phandle = < 0xa >;
    			group1 {
    				psels = < 0x40028 >, < 0x6002a >, < 0x50029 >;
    				low-power-enable;
    			};
    		};
    		spi2_default: spi2_default {
    			phandle = < 0xb >;
    			group1 {
    				psels = < 0x4002c >, < 0x6002e >, < 0x5002d >;
    			};
    		};
    		spi2_sleep: spi2_sleep {
    			phandle = < 0xc >;
    			group1 {
    				psels = < 0x4002c >, < 0x6002e >, < 0x5002d >;
    				low-power-enable;
    			};
    		};
    	};
    	rng_hci: entropy_bt_hci {
    		compatible = "zephyr,bt-hci-entropy";
    		status = "okay";
    	};
    	cpus {
    		#address-cells = < 0x1 >;
    		#size-cells = < 0x0 >;
    		cpu0: cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-m33f";
    			reg = < 0x0 >;
    			#address-cells = < 0x1 >;
    			#size-cells = < 0x1 >;
    			itm: itm@e0000000 {
    				compatible = "arm,armv8m-itm";
    				reg = < 0xe0000000 0x1000 >;
    				swo-ref-frequency = < 0x3d09000 >;
    			};
    			mpu: mpu@e000ed90 {
    				compatible = "arm,armv8m-mpu";
    				reg = < 0xe000ed90 0x40 >;
    				arm,num-mpu-regions = < 0x8 >;
    			};
    		};
    	};
    	ipc {
    		ipc0: ipc0 {
    			compatible = "zephyr,ipc-openamp-static-vrings";
    			memory-region = < &sram0_shared >;
    			mboxes = < &mbox 0x0 >, < &mbox 0x1 >;
    			mbox-names = "tx", "rx";
    			role = "host";
    			status = "okay";
    		};
    	};
    	leds {
    		compatible = "gpio-leds";
    		led0: led_0 {
    			gpios = < &gpio0 0x1c 0x0 >;
    			label = "Led Red";
    		};
    		led1: led_1 {
    			gpios = < &gpio0 0x1d 0x0 >;
    			label = "Led Blue";
    		};
    		led2: led_2 {
    			gpios = < &gpio0 0x1e 0x0 >;
    			label = "Led Green";
    		};
    		led3: led_3 {
    			gpios = < &gpio0 0x1f 0x1 >;
    			label = "Green LED 3";
    		};
    	};
    	pwmleds {
    		compatible = "pwm-leds";
    		pwm_led0: pwm_led_0 {
    			pwms = < &pwm0 0x0 0x1312d00 0x1 >;
    		};
    	};
    	buttons {
    		compatible = "gpio-keys";
    		button0: button_0 {
    			gpios = < &gpio0 0x19 0x0 >;
    			label = "MCP25 INT IRQ Pin";
    		};
    		button1: button_1 {
    			gpios = < &gpio0 0x1a 0x0 >;
    			label = "MCP25 INT0 IRQ Pin";
    		};
    		button2: button_2 {
    			gpios = < &gpio0 0x1b 0x0 >;
    			label = "MCP25 INT1 IRQ Pin";
    		};
    		button3: button_3 {
    			gpios = < &gpio0 0x9 0x11 >;
    			label = "Push button 4";
    		};
    	};
    	arduino_header: connector {
    		compatible = "arduino-header-r3";
    		#gpio-cells = < 0x2 >;
    		gpio-map-mask = < 0xffffffff 0xffffffc0 >;
    		gpio-map-pass-thru = < 0x0 0x3f >;
    		gpio-map = < 0x0 0x0 &gpio0 0x4 0x0 >, < 0x1 0x0 &gpio0 0x5 0x0 >, < 0x2 0x0 &gpio0 0x6 0x0 >, < 0x3 0x0 &gpio0 0x7 0x0 >, < 0x4 0x0 &gpio0 0x19 0x0 >, < 0x5 0x0 &gpio0 0x1a 0x0 >, < 0x6 0x0 &gpio1 0x0 0x0 >, < 0x7 0x0 &gpio1 0x1 0x0 >, < 0x8 0x0 &gpio1 0x4 0x0 >, < 0x9 0x0 &gpio1 0x5 0x0 >, < 0xa 0x0 &gpio1 0x6 0x0 >, < 0xb 0x0 &gpio1 0x7 0x0 >, < 0xc 0x0 &gpio1 0x8 0x0 >, < 0xd 0x0 &gpio1 0x9 0x0 >, < 0xe 0x0 &gpio1 0xa 0x0 >, < 0xf 0x0 &gpio1 0xb 0x0 >, < 0x10 0x0 &gpio1 0xc 0x0 >, < 0x11 0x0 &gpio1 0xd 0x0 >, < 0x12 0x0 &gpio1 0xe 0x0 >, < 0x13 0x0 &gpio1 0xf 0x0 >, < 0x14 0x0 &gpio1 0x2 0x0 >, < 0x15 0x0 &gpio1 0x3 0x0 >;
    	};
    	arduino_adc: analog-connector {
    		compatible = "arduino,uno-adc";
    		#io-channel-cells = < 0x1 >;
    		io-channel-map = < 0x0 &adc 0x0 >, < 0x1 &adc 0x1 >, < 0x2 &adc 0x2 >, < 0x3 &adc 0x3 >, < 0x4 &adc 0x4 >, < 0x5 &adc 0x5 >;
    	};
    	gpio_fwd: nrf-gpio-forwarder {
    		compatible = "nordic,nrf-gpio-forwarder";
    		status = "okay";
    		uart {
    			gpios = < &gpio1 0x1 0x0 >, < &gpio1 0x0 0x0 >, < &gpio0 0xb 0x0 >, < &gpio0 0xa 0x0 >;
    		};
    	};
    	reserved-memory {
    		#address-cells = < 0x1 >;
    		#size-cells = < 0x1 >;
    		ranges;
    		sram0_image: image@20000000 {
    			reg = < 0x20000000 0x70000 >;
    		};
    		sram0_s: image_s@20000000 {
    			reg = < 0x20000000 0x40000 >;
    		};
    		sram0_ns: image_ns@20040000 {
    			reg = < 0x20040000 0x30000 >;
    		};
    		sram0_shared: memory@20070000 {
    			reg = < 0x20070000 0x10000 >;
    			phandle = < 0x11 >;
    		};
    	};
    };
    

    devicetree_generated.h:

    /*
     * Generated by gen_defines.py
     *
     * DTS input file:
     *   C:/Projekte/BleCan_CAB11A/build/zephyr/zephyr.dts.pre
     *
     * Directories with bindings:
     *   C:/DevTools/ncs/v2.4.2/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
     *
     * Node dependency ordering (ordinal and path):
     *   0   /
     *   1   /aliases
     *   2   /analog-connector
     *   3   /chosen
     *   4   /connector
     *   5   /entropy_bt_hci
     *   6   /buttons
     *   7   /soc
     *   8   /soc/peripheral@50000000
     *   9   /soc/peripheral@50000000/gpio@842500
     *   10  /buttons/button_0
     *   11  /buttons/button_1
     *   12  /buttons/button_2
     *   13  /buttons/button_3
     *   14  /cpus
     *   15  /cpus/cpu@0
     *   16  /cpus/cpu@0/itm@e0000000
     *   17  /cpus/cpu@0/mpu@e000ed90
     *   18  /ipc
     *   19  /reserved-memory
     *   20  /reserved-memory/memory@20070000
     *   21  /soc/interrupt-controller@e000e100
     *   22  /soc/peripheral@50000000/mbox@2a000
     *   23  /ipc/ipc0
     *   24  /leds
     *   25  /leds/led_0
     *   26  /leds/led_1
     *   27  /leds/led_2
     *   28  /leds/led_3
     *   29  /nrf-gpio-forwarder
     *   30  /soc/peripheral@50000000/gpio@842800
     *   31  /nrf-gpio-forwarder/uart
     *   32  /pin-controller
     *   33  /pin-controller/i2c1_default
     *   34  /pin-controller/i2c1_default/group1
     *   35  /pin-controller/i2c1_sleep
     *   36  /pin-controller/i2c1_sleep/group1
     *   37  /pin-controller/pwm0_default
     *   38  /pin-controller/pwm0_default/group1
     *   39  /pin-controller/pwm0_sleep
     *   40  /pin-controller/pwm0_sleep/group1
     *   41  /pin-controller/qspi_default
     *   42  /pin-controller/qspi_default/group1
     *   43  /pin-controller/qspi_sleep
     *   44  /pin-controller/qspi_sleep/group1
     *   45  /pin-controller/qspi_sleep/group2
     *   46  /pin-controller/spi2_default
     *   47  /pin-controller/spi2_default/group1
     *   48  /pin-controller/spi2_sleep
     *   49  /pin-controller/spi2_sleep/group1
     *   50  /pin-controller/spi4_default
     *   51  /pin-controller/spi4_default/group1
     *   52  /pin-controller/spi4_sleep
     *   53  /pin-controller/spi4_sleep/group1
     *   54  /pin-controller/uart0_default
     *   55  /pin-controller/uart0_default/group1
     *   56  /pin-controller/uart0_default/group2
     *   57  /pin-controller/uart0_sleep
     *   58  /pin-controller/uart0_sleep/group1
     *   59  /pin-controller/uart1_default
     *   60  /pin-controller/uart1_default/group1
     *   61  /pin-controller/uart1_default/group2
     *   62  /pin-controller/uart1_sleep
     *   63  /pin-controller/uart1_sleep/group1
     *   64  /pwmleds
     *   65  /soc/peripheral@50000000/pwm@21000
     *   66  /pwmleds/pwm_led_0
     *   67  /reserved-memory/image@20000000
     *   68  /reserved-memory/image_ns@20040000
     *   69  /reserved-memory/image_s@20000000
     *   70  /soc/ficr@ff0000
     *   71  /soc/gpiote@4002f000
     *   72  /soc/gpiote@5000d000
     *   73  /soc/memory@20000000
     *   74  /soc/spu@50003000
     *   75  /soc/timer@e000e010
     *   76  /soc/uicr@ff8000
     *   77  /soc/crypto@50844000
     *   78  /soc/crypto@50844000/crypto@50845000
     *   79  /soc/peripheral@50000000/adc@e000
     *   80  /soc/peripheral@50000000/clock@5000
     *   81  /soc/peripheral@50000000/comparator@1a000
     *   82  /soc/peripheral@50000000/ctrlap@6000
     *   83  /soc/peripheral@50000000/dcnf@0
     *   84  /soc/peripheral@50000000/dppic@17000
     *   85  /soc/peripheral@50000000/egu@1b000
     *   86  /soc/peripheral@50000000/egu@1c000
     *   87  /soc/peripheral@50000000/egu@1d000
     *   88  /soc/peripheral@50000000/egu@1e000
     *   89  /soc/peripheral@50000000/egu@1f000
     *   90  /soc/peripheral@50000000/egu@20000
     *   91  /soc/peripheral@50000000/i2c@8000
     *   92  /soc/peripheral@50000000/i2c@b000
     *   93  /soc/peripheral@50000000/i2c@c000
     *   94  /soc/peripheral@50000000/i2s@28000
     *   95  /soc/peripheral@50000000/ieee802154
     *   96  /soc/peripheral@50000000/kmu@39000
     *   97  /soc/peripheral@50000000/mutex@30000
     *   98  /soc/peripheral@50000000/nfct@2d000
     *   99  /soc/peripheral@50000000/oscillator@4000
     *   100 /soc/peripheral@50000000/pdm@26000
     *   101 /soc/peripheral@50000000/pwm@22000
     *   102 /soc/peripheral@50000000/pwm@23000
     *   103 /soc/peripheral@50000000/pwm@24000
     *   104 /soc/peripheral@50000000/qdec@33000
     *   105 /soc/peripheral@50000000/qdec@34000
     *   106 /soc/peripheral@50000000/regulator@4000
     *   107 /soc/peripheral@50000000/regulator@37000
     *   108 /soc/peripheral@50000000/reset-controller@5000
     *   109 /soc/peripheral@50000000/rtc@14000
     *   110 /soc/peripheral@50000000/rtc@15000
     *   111 /soc/peripheral@50000000/spi@8000
     *   112 /soc/peripheral@50000000/spi@9000
     *   113 /soc/peripheral@50000000/spi@a000
     *   114 /soc/peripheral@50000000/spi@c000
     *   115 /soc/peripheral@50000000/timer@f000
     *   116 /soc/peripheral@50000000/timer@10000
     *   117 /soc/peripheral@50000000/timer@11000
     *   118 /soc/peripheral@50000000/uart@8000
     *   119 /soc/peripheral@50000000/uart@9000
     *   120 /soc/peripheral@50000000/uart@b000
     *   121 /soc/peripheral@50000000/uart@c000
     *   122 /soc/peripheral@50000000/usbd@36000
     *   123 /soc/peripheral@50000000/vmc@81000
     *   124 /soc/peripheral@50000000/watchdog@18000
     *   125 /soc/peripheral@50000000/watchdog@19000
     *   126 /soc/peripheral@50000000/flash-controller@39000
     *   127 /soc/peripheral@50000000/flash-controller@39000/flash@0
     *   128 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
     *   129 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
     *   130 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
     *   131 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000
     *   132 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
     *   133 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000
     *   134 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000
     *   135 /soc/peripheral@50000000/i2c@9000
     *   136 /soc/peripheral@50000000/i2c@9000/ST25V@1
     *   137 /soc/peripheral@50000000/power@5000
     *   138 /soc/peripheral@50000000/power@5000/gpregret1@551c
     *   139 /soc/peripheral@50000000/power@5000/gpregret2@5520
     *   140 /soc/peripheral@50000000/qspi@2b000
     *   141 /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0
     *   142 /soc/peripheral@50000000/spi@b000
     *   143 /soc/peripheral@50000000/spi@b000/mx25l16test@0
     *
     * Definitions derived from these nodes in dependency order are next,
     * followed by /chosen nodes.
     */
    
    /* Used to remove brackets from around a single argument */
    #define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__
    
    /*
     * Devicetree node: /
     *
     * Node identifier: DT_N
     */
    
    /* Node's full path: */
    #define DT_N_PATH "/"
    
    /* Node's name with unit-address: */
    #define DT_N_FULL_NAME "/"
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_reserved_memory)
    #define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
    #define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
    #define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)
    #define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_reserved_memory)
    #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
    #define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
    #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_ORD 0
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_REQUIRES_ORDS /* nothing */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_SUPPORTS_ORDS \
    	1, /* /aliases */ \
    	2, /* /analog-connector */ \
    	3, /* /chosen */ \
    	4, /* /connector */ \
    	5, /* /entropy_bt_hci */ \
    	6, /* /buttons */ \
    	7, /* /soc */ \
    	14, /* /cpus */ \
    	18, /* /ipc */ \
    	19, /* /reserved-memory */ \
    	24, /* /leds */ \
    	29, /* /nrf-gpio-forwarder */ \
    	32, /* /pin-controller */ \
    	64, /* /pwmleds */
    
    /* Existence and alternate IDs: */
    #define DT_N_EXISTS 1
    #define DT_N_INST_0_nordic_nrf5340_dk_nrf5340_cpuapp DT_N
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_REG_NUM 0
    #define DT_N_RANGES_NUM 0
    #define DT_N_FOREACH_RANGE(fn) 
    #define DT_N_IRQ_NUM 0
    #define DT_N_COMPAT_MATCHES_nordic_nrf5340_dk_nrf5340_cpuapp 1
    #define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_COMPAT_MODEL_IDX_0 "nrf5340-dk-nrf5340-cpuapp"
    #define DT_N_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_P_compatible {"nordic,nrf5340-dk-nrf5340-cpuapp"}
    #define DT_N_P_compatible_IDX_0 "nordic,nrf5340-dk-nrf5340-cpuapp"
    #define DT_N_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5340-dk-nrf5340-cpuapp
    #define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5340_dk_nrf5340_cpuapp
    #define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5340_DK_NRF5340_CPUAPP
    #define DT_N_P_compatible_IDX_0_EXISTS 1
    #define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
    #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
    #define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
    #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
    #define DT_N_P_compatible_LEN 1
    #define DT_N_P_compatible_EXISTS 1
    
    /*
     * Devicetree node: /aliases
     *
     * Node identifier: DT_N_S_aliases
     */
    
    /* Node's full path: */
    #define DT_N_S_aliases_PATH "/aliases"
    
    /* Node's name with unit-address: */
    #define DT_N_S_aliases_FULL_NAME "aliases"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_aliases_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_aliases_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_aliases_FOREACH_CHILD(fn) 
    #define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_aliases_ORD 1
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_aliases_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_aliases_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_aliases_REG_NUM 0
    #define DT_N_S_aliases_RANGES_NUM 0
    #define DT_N_S_aliases_FOREACH_RANGE(fn) 
    #define DT_N_S_aliases_IRQ_NUM 0
    #define DT_N_S_aliases_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_aliases_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /analog-connector
     *
     * Node identifier: DT_N_S_analog_connector
     *
     * Binding (compatible = arduino,uno-adc):
     *   $ZEPHYR_BASE\dts\bindings\adc\arduino,uno-adc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_analog_connector_PATH "/analog-connector"
    
    /* Node's name with unit-address: */
    #define DT_N_S_analog_connector_FULL_NAME "analog-connector"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_analog_connector_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_analog_connector_CHILD_IDX 11
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_analog_connector_FOREACH_CHILD(fn) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_analog_connector_ORD 2
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_analog_connector_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_analog_connector_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_analog_connector_EXISTS 1
    #define DT_N_INST_0_arduino_uno_adc DT_N_S_analog_connector
    #define DT_N_NODELABEL_arduino_adc  DT_N_S_analog_connector
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_analog_connector_REG_NUM 0
    #define DT_N_S_analog_connector_RANGES_NUM 0
    #define DT_N_S_analog_connector_FOREACH_RANGE(fn) 
    #define DT_N_S_analog_connector_IRQ_NUM 0
    #define DT_N_S_analog_connector_COMPAT_MATCHES_arduino_uno_adc 1
    #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0 "Arduino"
    #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0 "uno-adc"
    #define DT_N_S_analog_connector_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_analog_connector_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_analog_connector_P_compatible {"arduino,uno-adc"}
    #define DT_N_S_analog_connector_P_compatible_IDX_0 "arduino,uno-adc"
    #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino,uno-adc
    #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_TOKEN arduino_uno_adc
    #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_UNO_ADC
    #define DT_N_S_analog_connector_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_analog_connector, compatible, 0)
    #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_analog_connector, compatible, 0)
    #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__)
    #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__)
    #define DT_N_S_analog_connector_P_compatible_LEN 1
    #define DT_N_S_analog_connector_P_compatible_EXISTS 1
    #define DT_N_S_analog_connector_P_wakeup_source 0
    #define DT_N_S_analog_connector_P_wakeup_source_EXISTS 1
    #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /chosen
     *
     * Node identifier: DT_N_S_chosen
     */
    
    /* Node's full path: */
    #define DT_N_S_chosen_PATH "/chosen"
    
    /* Node's name with unit-address: */
    #define DT_N_S_chosen_FULL_NAME "chosen"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_chosen_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_chosen_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_chosen_FOREACH_CHILD(fn) 
    #define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_chosen_ORD 3
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_chosen_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_chosen_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_chosen_REG_NUM 0
    #define DT_N_S_chosen_RANGES_NUM 0
    #define DT_N_S_chosen_FOREACH_RANGE(fn) 
    #define DT_N_S_chosen_IRQ_NUM 0
    #define DT_N_S_chosen_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_chosen_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /connector
     *
     * Node identifier: DT_N_S_connector
     *
     * Binding (compatible = arduino-header-r3):
     *   $ZEPHYR_BASE\dts\bindings\gpio\arduino-header-r3.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_connector_PATH "/connector"
    
    /* Node's name with unit-address: */
    #define DT_N_S_connector_FULL_NAME "connector"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_connector_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_connector_CHILD_IDX 10
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_connector_FOREACH_CHILD(fn) 
    #define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_connector_ORD 4
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_connector_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_connector_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_connector_EXISTS 1
    #define DT_N_INST_0_arduino_header_r3 DT_N_S_connector
    #define DT_N_NODELABEL_arduino_header DT_N_S_connector
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_connector_REG_NUM 0
    #define DT_N_S_connector_RANGES_NUM 0
    #define DT_N_S_connector_FOREACH_RANGE(fn) 
    #define DT_N_S_connector_IRQ_NUM 0
    #define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1
    #define DT_N_S_connector_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_connector_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_connector_P_compatible {"arduino-header-r3"}
    #define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3"
    #define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3
    #define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3
    #define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3
    #define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0)
    #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0)
    #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
    #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
    #define DT_N_S_connector_P_compatible_LEN 1
    #define DT_N_S_connector_P_compatible_EXISTS 1
    #define DT_N_S_connector_P_wakeup_source 0
    #define DT_N_S_connector_P_wakeup_source_EXISTS 1
    #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /entropy_bt_hci
     *
     * Node identifier: DT_N_S_entropy_bt_hci
     *
     * Binding (compatible = zephyr,bt-hci-entropy):
     *   $ZEPHYR_BASE\dts\bindings\bluetooth\zephyr,bt-hci-entropy.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci"
    
    /* Node's name with unit-address: */
    #define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_entropy_bt_hci_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_entropy_bt_hci_CHILD_IDX 4
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_entropy_bt_hci_ORD 5
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_entropy_bt_hci_EXISTS 1
    #define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci
    #define DT_N_NODELABEL_rng_hci            DT_N_S_entropy_bt_hci
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_entropy_bt_hci_REG_NUM 0
    #define DT_N_S_entropy_bt_hci_RANGES_NUM 0
    #define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) 
    #define DT_N_S_entropy_bt_hci_IRQ_NUM 0
    #define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1
    #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
    #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy"
    #define DT_N_S_entropy_bt_hci_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_entropy_bt_hci_P_status "okay"
    #define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay
    #define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay
    #define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1
    #define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay
    #define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0) \
    	fn(DT_N_S_entropy_bt_hci, status, 1) \
    	fn(DT_N_S_entropy_bt_hci, status, 2) \
    	fn(DT_N_S_entropy_bt_hci, status, 3)
    #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 3)
    #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_entropy_bt_hci, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_entropy_bt_hci, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_entropy_bt_hci, status, 3, __VA_ARGS__)
    #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_entropy_bt_hci, status, 3, __VA_ARGS__)
    #define DT_N_S_entropy_bt_hci_P_status_EXISTS 1
    #define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"}
    #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy"
    #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy
    #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy
    #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY
    #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0)
    #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0)
    #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
    #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
    #define DT_N_S_entropy_bt_hci_P_compatible_LEN 1
    #define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1
    #define DT_N_S_entropy_bt_hci_P_wakeup_source 0
    #define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1
    #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /buttons
     *
     * Node identifier: DT_N_S_buttons
     *
     * Binding (compatible = gpio-keys):
     *   $ZEPHYR_BASE\dts\bindings\input\gpio-keys.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_buttons_PATH "/buttons"
    
    /* Node's name with unit-address: */
    #define DT_N_S_buttons_FULL_NAME "buttons"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_buttons_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_buttons_CHILD_IDX 9
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
    #define DT_N_S_buttons_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
    #define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
    #define DT_N_S_buttons_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
    #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
    #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
    #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
    #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_buttons_ORD 6
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_buttons_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_buttons_SUPPORTS_ORDS \
    	10, /* /buttons/button_0 */ \
    	11, /* /buttons/button_1 */ \
    	12, /* /buttons/button_2 */ \
    	13, /* /buttons/button_3 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_buttons_EXISTS 1
    #define DT_N_INST_0_gpio_keys DT_N_S_buttons
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_buttons_REG_NUM 0
    #define DT_N_S_buttons_RANGES_NUM 0
    #define DT_N_S_buttons_FOREACH_RANGE(fn) 
    #define DT_N_S_buttons_IRQ_NUM 0
    #define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1
    #define DT_N_S_buttons_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_buttons_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_buttons_P_debounce_interval_ms 30
    #define DT_N_S_buttons_P_debounce_interval_ms_EXISTS 1
    #define DT_N_S_buttons_P_compatible {"gpio-keys"}
    #define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys"
    #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys
    #define DT_N_S_buttons_P_compatible_IDX_0_STRING_TOKEN gpio_keys
    #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS
    #define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons, compatible, 0)
    #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons, compatible, 0)
    #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
    #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
    #define DT_N_S_buttons_P_compatible_LEN 1
    #define DT_N_S_buttons_P_compatible_EXISTS 1
    #define DT_N_S_buttons_P_wakeup_source 0
    #define DT_N_S_buttons_P_wakeup_source_EXISTS 1
    #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc
     *
     * Node identifier: DT_N_S_soc
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_PATH "/soc"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_FULL_NAME "soc"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_soc_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_gpiote_4002f000)
    #define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000)
    #define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__)
    #define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__)
    #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000)
    #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000)
    #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__)
    #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_ORD 7
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_SUPPORTS_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	70, /* /soc/ficr@ff0000 */ \
    	71, /* /soc/gpiote@4002f000 */ \
    	72, /* /soc/gpiote@5000d000 */ \
    	73, /* /soc/memory@20000000 */ \
    	74, /* /soc/spu@50003000 */ \
    	75, /* /soc/timer@e000e010 */ \
    	76, /* /soc/uicr@ff8000 */ \
    	77, /* /soc/crypto@50844000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_EXISTS 1
    #define DT_N_INST_0_nordic_nrf5340_cpuapp_qkaa DT_N_S_soc
    #define DT_N_INST_0_nordic_nrf5340_cpuapp      DT_N_S_soc
    #define DT_N_INST_0_nordic_nrf53               DT_N_S_soc
    #define DT_N_INST_0_simple_bus                 DT_N_S_soc
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_REG_NUM 0
    #define DT_N_S_soc_RANGES_NUM 0
    #define DT_N_S_soc_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_IRQ_NUM 0
    #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp_qkaa 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nRF5340-CPUAPP-QKAA"
    #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
    #define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
    #define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nRF5340-CPUAPP"
    #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf53 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1
    #define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor"
    #define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1
    #define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nRF53"
    #define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
    #define DT_N_S_soc_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_P_compatible {"nordic,nRF5340-CPUAPP-QKAA", "nordic,nRF5340-CPUAPP", "nordic,nRF53", "simple-bus"}
    #define DT_N_S_soc_P_compatible_IDX_0 "nordic,nRF5340-CPUAPP-QKAA"
    #define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED nordic,nRF5340-CPUAPP-QKAA
    #define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nRF5340_CPUAPP_QKAA
    #define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP_QKAA
    #define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_P_compatible_IDX_1 "nordic,nRF5340-CPUAPP"
    #define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED nordic,nRF5340-CPUAPP
    #define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nRF5340_CPUAPP
    #define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP
    #define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
    #define DT_N_S_soc_P_compatible_IDX_2 "nordic,nRF53"
    #define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED nordic,nRF53
    #define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nRF53
    #define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF53
    #define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
    #define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
    #define DT_N_S_soc_P_compatible_IDX_3_STRING_UNQUOTED simple-bus
    #define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus
    #define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS
    #define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
    #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
    	fn(DT_N_S_soc, compatible, 1) \
    	fn(DT_N_S_soc, compatible, 2) \
    	fn(DT_N_S_soc, compatible, 3)
    #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 3)
    #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
    #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
    #define DT_N_S_soc_P_compatible_LEN 4
    #define DT_N_S_soc_P_compatible_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_PATH "/soc/peripheral@50000000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME "peripheral@50000000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_CHILD_IDX 5
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_ORD 8
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_SUPPORTS_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	22, /* /soc/peripheral@50000000/mbox@2a000 */ \
    	30, /* /soc/peripheral@50000000/gpio@842800 */ \
    	65, /* /soc/peripheral@50000000/pwm@21000 */ \
    	79, /* /soc/peripheral@50000000/adc@e000 */ \
    	80, /* /soc/peripheral@50000000/clock@5000 */ \
    	81, /* /soc/peripheral@50000000/comparator@1a000 */ \
    	82, /* /soc/peripheral@50000000/ctrlap@6000 */ \
    	83, /* /soc/peripheral@50000000/dcnf@0 */ \
    	84, /* /soc/peripheral@50000000/dppic@17000 */ \
    	85, /* /soc/peripheral@50000000/egu@1b000 */ \
    	86, /* /soc/peripheral@50000000/egu@1c000 */ \
    	87, /* /soc/peripheral@50000000/egu@1d000 */ \
    	88, /* /soc/peripheral@50000000/egu@1e000 */ \
    	89, /* /soc/peripheral@50000000/egu@1f000 */ \
    	90, /* /soc/peripheral@50000000/egu@20000 */ \
    	91, /* /soc/peripheral@50000000/i2c@8000 */ \
    	92, /* /soc/peripheral@50000000/i2c@b000 */ \
    	93, /* /soc/peripheral@50000000/i2c@c000 */ \
    	94, /* /soc/peripheral@50000000/i2s@28000 */ \
    	95, /* /soc/peripheral@50000000/ieee802154 */ \
    	96, /* /soc/peripheral@50000000/kmu@39000 */ \
    	97, /* /soc/peripheral@50000000/mutex@30000 */ \
    	98, /* /soc/peripheral@50000000/nfct@2d000 */ \
    	99, /* /soc/peripheral@50000000/oscillator@4000 */ \
    	100, /* /soc/peripheral@50000000/pdm@26000 */ \
    	101, /* /soc/peripheral@50000000/pwm@22000 */ \
    	102, /* /soc/peripheral@50000000/pwm@23000 */ \
    	103, /* /soc/peripheral@50000000/pwm@24000 */ \
    	104, /* /soc/peripheral@50000000/qdec@33000 */ \
    	105, /* /soc/peripheral@50000000/qdec@34000 */ \
    	106, /* /soc/peripheral@50000000/regulator@4000 */ \
    	107, /* /soc/peripheral@50000000/regulator@37000 */ \
    	108, /* /soc/peripheral@50000000/reset-controller@5000 */ \
    	109, /* /soc/peripheral@50000000/rtc@14000 */ \
    	110, /* /soc/peripheral@50000000/rtc@15000 */ \
    	111, /* /soc/peripheral@50000000/spi@8000 */ \
    	112, /* /soc/peripheral@50000000/spi@9000 */ \
    	113, /* /soc/peripheral@50000000/spi@a000 */ \
    	114, /* /soc/peripheral@50000000/spi@c000 */ \
    	115, /* /soc/peripheral@50000000/timer@f000 */ \
    	116, /* /soc/peripheral@50000000/timer@10000 */ \
    	117, /* /soc/peripheral@50000000/timer@11000 */ \
    	118, /* /soc/peripheral@50000000/uart@8000 */ \
    	119, /* /soc/peripheral@50000000/uart@9000 */ \
    	120, /* /soc/peripheral@50000000/uart@b000 */ \
    	121, /* /soc/peripheral@50000000/uart@c000 */ \
    	122, /* /soc/peripheral@50000000/usbd@36000 */ \
    	123, /* /soc/peripheral@50000000/vmc@81000 */ \
    	124, /* /soc/peripheral@50000000/watchdog@18000 */ \
    	125, /* /soc/peripheral@50000000/watchdog@19000 */ \
    	126, /* /soc/peripheral@50000000/flash-controller@39000 */ \
    	135, /* /soc/peripheral@50000000/i2c@9000 */ \
    	137, /* /soc/peripheral@50000000/power@5000 */ \
    	140, /* /soc/peripheral@50000000/qspi@2b000 */ \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_RANGES_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
    #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1342177280 /* 0x50000000 */
    #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */
    #define DT_N_S_soc_S_peripheral_50000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000, 0)
    #define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /soc/peripheral@50000000/gpio@842500
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
     *
     * Binding (compatible = nordic,nrf-gpio):
     *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PATH "/soc/peripheral@50000000/gpio@842500"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME "gpio@842500"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_IDX 53
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD 9
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_SUPPORTS_ORDS \
    	10, /* /buttons/button_0 */ \
    	11, /* /buttons/button_1 */ \
    	12, /* /buttons/button_2 */ \
    	13, /* /buttons/button_3 */ \
    	25, /* /leds/led_0 */ \
    	26, /* /leds/led_1 */ \
    	27, /* /leds/led_2 */ \
    	28, /* /leds/led_3 */ \
    	31, /* /nrf-gpio-forwarder/uart */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0 "nrf-gpio"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"}
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /buttons/button_0
     *
     * Node identifier: DT_N_S_buttons_S_button_0
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_buttons_S_button_0_PATH "/buttons/button_0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_buttons_S_button_0_FULL_NAME "button_0"
    
    /* Node parent (/buttons) identifier: */
    #define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_buttons_S_button_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_buttons_S_button_0_ORD 10
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \
    	6, /* /buttons */ \
    	9, /* /soc/peripheral@50000000/gpio@842500 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_buttons_S_button_0_EXISTS 1
    #define DT_N_ALIAS_sw0             DT_N_S_buttons_S_button_0
    #define DT_N_ALIAS_mcuboot_button0 DT_N_S_buttons_S_button_0
    #define DT_N_NODELABEL_button0     DT_N_S_buttons_S_button_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_buttons_S_button_0_REG_NUM 0
    #define DT_N_S_buttons_S_button_0_RANGES_NUM 0
    #define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn) 
    #define DT_N_S_buttons_S_button_0_IRQ_NUM 0
    #define DT_N_S_buttons_S_button_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_buttons_S_button_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 25
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, gpios, 0)
    #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, gpios, 0)
    #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_0_P_gpios_LEN 1
    #define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1
    #define DT_N_S_buttons_S_button_0_P_label "MCP25 INT IRQ Pin"
    #define DT_N_S_buttons_S_button_0_P_label_STRING_UNQUOTED MCP25 INT IRQ Pin
    #define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN MCP25_INT_IRQ_Pin
    #define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN MCP25_INT_IRQ_PIN
    #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, label, 0) \
    	fn(DT_N_S_buttons_S_button_0, label, 1) \
    	fn(DT_N_S_buttons_S_button_0, label, 2) \
    	fn(DT_N_S_buttons_S_button_0, label, 3) \
    	fn(DT_N_S_buttons_S_button_0, label, 4) \
    	fn(DT_N_S_buttons_S_button_0, label, 5) \
    	fn(DT_N_S_buttons_S_button_0, label, 6) \
    	fn(DT_N_S_buttons_S_button_0, label, 7) \
    	fn(DT_N_S_buttons_S_button_0, label, 8) \
    	fn(DT_N_S_buttons_S_button_0, label, 9) \
    	fn(DT_N_S_buttons_S_button_0, label, 10) \
    	fn(DT_N_S_buttons_S_button_0, label, 11) \
    	fn(DT_N_S_buttons_S_button_0, label, 12) \
    	fn(DT_N_S_buttons_S_button_0, label, 13) \
    	fn(DT_N_S_buttons_S_button_0, label, 14) \
    	fn(DT_N_S_buttons_S_button_0, label, 15) \
    	fn(DT_N_S_buttons_S_button_0, label, 16)
    #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 16)
    #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 12, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 13, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 14, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 15, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_0, label, 16, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_0, label, 16, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_0_P_label_EXISTS 1
    #define DT_N_S_buttons_S_button_0_P_zephyr_code 0
    #define DT_N_S_buttons_S_button_0_P_zephyr_code_EXISTS 1
    
    /*
     * Devicetree node: /buttons/button_1
     *
     * Node identifier: DT_N_S_buttons_S_button_1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_buttons_S_button_1_PATH "/buttons/button_1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_buttons_S_button_1_FULL_NAME "button_1"
    
    /* Node parent (/buttons) identifier: */
    #define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_buttons_S_button_1_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_buttons_S_button_1_ORD 11
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \
    	6, /* /buttons */ \
    	9, /* /soc/peripheral@50000000/gpio@842500 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_buttons_S_button_1_EXISTS 1
    #define DT_N_ALIAS_sw1         DT_N_S_buttons_S_button_1
    #define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_buttons_S_button_1_REG_NUM 0
    #define DT_N_S_buttons_S_button_1_RANGES_NUM 0
    #define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn) 
    #define DT_N_S_buttons_S_button_1_IRQ_NUM 0
    #define DT_N_S_buttons_S_button_1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_buttons_S_button_1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 26
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, gpios, 0)
    #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, gpios, 0)
    #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_1_P_gpios_LEN 1
    #define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1
    #define DT_N_S_buttons_S_button_1_P_label "MCP25 INT0 IRQ Pin"
    #define DT_N_S_buttons_S_button_1_P_label_STRING_UNQUOTED MCP25 INT0 IRQ Pin
    #define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN MCP25_INT0_IRQ_Pin
    #define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN MCP25_INT0_IRQ_PIN
    #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, label, 0) \
    	fn(DT_N_S_buttons_S_button_1, label, 1) \
    	fn(DT_N_S_buttons_S_button_1, label, 2) \
    	fn(DT_N_S_buttons_S_button_1, label, 3) \
    	fn(DT_N_S_buttons_S_button_1, label, 4) \
    	fn(DT_N_S_buttons_S_button_1, label, 5) \
    	fn(DT_N_S_buttons_S_button_1, label, 6) \
    	fn(DT_N_S_buttons_S_button_1, label, 7) \
    	fn(DT_N_S_buttons_S_button_1, label, 8) \
    	fn(DT_N_S_buttons_S_button_1, label, 9) \
    	fn(DT_N_S_buttons_S_button_1, label, 10) \
    	fn(DT_N_S_buttons_S_button_1, label, 11) \
    	fn(DT_N_S_buttons_S_button_1, label, 12) \
    	fn(DT_N_S_buttons_S_button_1, label, 13) \
    	fn(DT_N_S_buttons_S_button_1, label, 14) \
    	fn(DT_N_S_buttons_S_button_1, label, 15) \
    	fn(DT_N_S_buttons_S_button_1, label, 16) \
    	fn(DT_N_S_buttons_S_button_1, label, 17)
    #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 16) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 17)
    #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 12, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 13, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 14, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 15, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 16, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_1, label, 17, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_1, label, 17, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_1_P_label_EXISTS 1
    #define DT_N_S_buttons_S_button_1_P_zephyr_code 0
    #define DT_N_S_buttons_S_button_1_P_zephyr_code_EXISTS 1
    
    /*
     * Devicetree node: /buttons/button_2
     *
     * Node identifier: DT_N_S_buttons_S_button_2
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_buttons_S_button_2_PATH "/buttons/button_2"
    
    /* Node's name with unit-address: */
    #define DT_N_S_buttons_S_button_2_FULL_NAME "button_2"
    
    /* Node parent (/buttons) identifier: */
    #define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_buttons_S_button_2_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_buttons_S_button_2_ORD 12
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \
    	6, /* /buttons */ \
    	9, /* /soc/peripheral@50000000/gpio@842500 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_buttons_S_button_2_EXISTS 1
    #define DT_N_ALIAS_sw2         DT_N_S_buttons_S_button_2
    #define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_buttons_S_button_2_REG_NUM 0
    #define DT_N_S_buttons_S_button_2_RANGES_NUM 0
    #define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn) 
    #define DT_N_S_buttons_S_button_2_IRQ_NUM 0
    #define DT_N_S_buttons_S_button_2_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_buttons_S_button_2_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 27
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, gpios, 0)
    #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, gpios, 0)
    #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_2_P_gpios_LEN 1
    #define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1
    #define DT_N_S_buttons_S_button_2_P_label "MCP25 INT1 IRQ Pin"
    #define DT_N_S_buttons_S_button_2_P_label_STRING_UNQUOTED MCP25 INT1 IRQ Pin
    #define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN MCP25_INT1_IRQ_Pin
    #define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN MCP25_INT1_IRQ_PIN
    #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, label, 0) \
    	fn(DT_N_S_buttons_S_button_2, label, 1) \
    	fn(DT_N_S_buttons_S_button_2, label, 2) \
    	fn(DT_N_S_buttons_S_button_2, label, 3) \
    	fn(DT_N_S_buttons_S_button_2, label, 4) \
    	fn(DT_N_S_buttons_S_button_2, label, 5) \
    	fn(DT_N_S_buttons_S_button_2, label, 6) \
    	fn(DT_N_S_buttons_S_button_2, label, 7) \
    	fn(DT_N_S_buttons_S_button_2, label, 8) \
    	fn(DT_N_S_buttons_S_button_2, label, 9) \
    	fn(DT_N_S_buttons_S_button_2, label, 10) \
    	fn(DT_N_S_buttons_S_button_2, label, 11) \
    	fn(DT_N_S_buttons_S_button_2, label, 12) \
    	fn(DT_N_S_buttons_S_button_2, label, 13) \
    	fn(DT_N_S_buttons_S_button_2, label, 14) \
    	fn(DT_N_S_buttons_S_button_2, label, 15) \
    	fn(DT_N_S_buttons_S_button_2, label, 16) \
    	fn(DT_N_S_buttons_S_button_2, label, 17)
    #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 16) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 17)
    #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 12, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 13, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 14, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 15, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 16, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_2, label, 17, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_2, label, 17, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_2_P_label_EXISTS 1
    #define DT_N_S_buttons_S_button_2_P_zephyr_code 0
    #define DT_N_S_buttons_S_button_2_P_zephyr_code_EXISTS 1
    
    /*
     * Devicetree node: /buttons/button_3
     *
     * Node identifier: DT_N_S_buttons_S_button_3
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_buttons_S_button_3_PATH "/buttons/button_3"
    
    /* Node's name with unit-address: */
    #define DT_N_S_buttons_S_button_3_FULL_NAME "button_3"
    
    /* Node parent (/buttons) identifier: */
    #define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_buttons_S_button_3_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_buttons_S_button_3_ORD 13
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \
    	6, /* /buttons */ \
    	9, /* /soc/peripheral@50000000/gpio@842500 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_buttons_S_button_3_EXISTS 1
    #define DT_N_ALIAS_sw3         DT_N_S_buttons_S_button_3
    #define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_buttons_S_button_3_REG_NUM 0
    #define DT_N_S_buttons_S_button_3_RANGES_NUM 0
    #define DT_N_S_buttons_S_button_3_FOREACH_RANGE(fn) 
    #define DT_N_S_buttons_S_button_3_IRQ_NUM 0
    #define DT_N_S_buttons_S_button_3_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_buttons_S_button_3_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 9
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17
    #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, gpios, 0)
    #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, gpios, 0)
    #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_3_P_gpios_LEN 1
    #define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1
    #define DT_N_S_buttons_S_button_3_P_label "Push button 4"
    #define DT_N_S_buttons_S_button_3_P_label_STRING_UNQUOTED Push button 4
    #define DT_N_S_buttons_S_button_3_P_label_STRING_TOKEN Push_button_4
    #define DT_N_S_buttons_S_button_3_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_4
    #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, label, 0) \
    	fn(DT_N_S_buttons_S_button_3, label, 1) \
    	fn(DT_N_S_buttons_S_button_3, label, 2) \
    	fn(DT_N_S_buttons_S_button_3, label, 3) \
    	fn(DT_N_S_buttons_S_button_3, label, 4) \
    	fn(DT_N_S_buttons_S_button_3, label, 5) \
    	fn(DT_N_S_buttons_S_button_3, label, 6) \
    	fn(DT_N_S_buttons_S_button_3, label, 7) \
    	fn(DT_N_S_buttons_S_button_3, label, 8) \
    	fn(DT_N_S_buttons_S_button_3, label, 9) \
    	fn(DT_N_S_buttons_S_button_3, label, 10) \
    	fn(DT_N_S_buttons_S_button_3, label, 11) \
    	fn(DT_N_S_buttons_S_button_3, label, 12)
    #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 12)
    #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_buttons_S_button_3, label, 12, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_buttons_S_button_3, label, 12, __VA_ARGS__)
    #define DT_N_S_buttons_S_button_3_P_label_EXISTS 1
    #define DT_N_S_buttons_S_button_3_P_zephyr_code 0
    #define DT_N_S_buttons_S_button_3_P_zephyr_code_EXISTS 1
    
    /*
     * Devicetree node: /cpus
     *
     * Node identifier: DT_N_S_cpus
     */
    
    /* Node's full path: */
    #define DT_N_S_cpus_PATH "/cpus"
    
    /* Node's name with unit-address: */
    #define DT_N_S_cpus_FULL_NAME "cpus"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_cpus_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_cpus_CHILD_IDX 5
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
    #define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
    #define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
    #define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
    #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0)
    #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
    #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
    #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_cpus_ORD 14
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_cpus_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_cpus_SUPPORTS_ORDS \
    	15, /* /cpus/cpu@0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_cpus_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_cpus_REG_NUM 0
    #define DT_N_S_cpus_RANGES_NUM 0
    #define DT_N_S_cpus_FOREACH_RANGE(fn) 
    #define DT_N_S_cpus_IRQ_NUM 0
    #define DT_N_S_cpus_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_cpus_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /cpus/cpu@0
     *
     * Node identifier: DT_N_S_cpus_S_cpu_0
     *
     * Binding (compatible = arm,cortex-m33f):
     *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m33f.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"
    
    /* Node parent (/cpus) identifier: */
    #define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_cpus_S_cpu_0_ORD 15
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
    	14, /* /cpus */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
    	16, /* /cpus/cpu@0/itm@e0000000 */ \
    	17, /* /cpus/cpu@0/mpu@e000ed90 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_cpus_S_cpu_0_EXISTS 1
    #define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0
    #define DT_N_NODELABEL_cpu0         DT_N_S_cpus_S_cpu_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_cpus_S_cpu_0_REG_NUM 1
    #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
    #define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
    #define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
    #define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
    #define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
    #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f"
    #define DT_N_S_cpus_S_cpu_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
    #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
    #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m33f
    #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f
    #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F
    #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
    #define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
    #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
    #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, reg, 0)
    #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, reg, 0)
    #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
    #define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /cpus/cpu@0/itm@e0000000
     *
     * Node identifier: DT_N_S_cpus_S_cpu_0_S_itm_e0000000
     *
     * Binding (compatible = arm,armv8m-itm):
     *   $ZEPHYR_BASE\dts\bindings\debug\arm,armv8m-itm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PATH "/cpus/cpu@0/itm@e0000000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME "itm@e0000000"
    
    /* Node parent (/cpus/cpu@0) identifier: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PARENT DT_N_S_cpus_S_cpu_0
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD 16
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REQUIRES_ORDS \
    	15, /* /cpus/cpu@0 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_EXISTS 1
    #define DT_N_INST_0_arm_armv8m_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000
    #define DT_N_NODELABEL_itm         DT_N_S_cpus_S_cpu_0_S_itm_e0000000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_NUM 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_ADDRESS 3758096384 /* 0xe0000000 */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_RANGES_NUM 0
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_RANGE(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_NUM 0
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MATCHES_arm_armv8m_itm 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0 "armv8m-itm"
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency 64000000
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible {"arm,armv8m-itm"}
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0 "arm,armv8m-itm"
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-itm
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_itm
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_ITM
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_LEN 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg {3758096384 /* 0xe0000000 */, 4096 /* 0x1000 */}
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0 3758096384
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1 4096
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 0) \
    	fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 1)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 1)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source 0
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /cpus/cpu@0/mpu@e000ed90
     *
     * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
     *
     * Binding (compatible = arm,armv8m-mpu):
     *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90"
    
    /* Node's name with unit-address: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90"
    
    /* Node parent (/cpus/cpu@0) identifier: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 17
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \
    	15, /* /cpus/cpu@0 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1
    #define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
    #define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) 
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0 "armv8m-mpu"
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0) \
    	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions 8
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-mpu
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_mpu
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_MPU
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /ipc
     *
     * Node identifier: DT_N_S_ipc
     */
    
    /* Node's full path: */
    #define DT_N_S_ipc_PATH "/ipc"
    
    /* Node's name with unit-address: */
    #define DT_N_S_ipc_FULL_NAME "ipc"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_ipc_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_ipc_CHILD_IDX 6
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_ipc_FOREACH_CHILD(fn) fn(DT_N_S_ipc_S_ipc0)
    #define DT_N_S_ipc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0)
    #define DT_N_S_ipc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
    #define DT_N_S_ipc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
    #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_ipc_S_ipc0)
    #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0)
    #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
    #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_ipc_ORD 18
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_ipc_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_ipc_SUPPORTS_ORDS \
    	23, /* /ipc/ipc0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_ipc_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_ipc_REG_NUM 0
    #define DT_N_S_ipc_RANGES_NUM 0
    #define DT_N_S_ipc_FOREACH_RANGE(fn) 
    #define DT_N_S_ipc_IRQ_NUM 0
    #define DT_N_S_ipc_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_ipc_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /reserved-memory
     *
     * Node identifier: DT_N_S_reserved_memory
     */
    
    /* Node's full path: */
    #define DT_N_S_reserved_memory_PATH "/reserved-memory"
    
    /* Node's name with unit-address: */
    #define DT_N_S_reserved_memory_FULL_NAME "reserved-memory"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_reserved_memory_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_reserved_memory_CHILD_IDX 13
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__)
    #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_reserved_memory_ORD 19
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_reserved_memory_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_reserved_memory_SUPPORTS_ORDS \
    	20, /* /reserved-memory/memory@20070000 */ \
    	67, /* /reserved-memory/image@20000000 */ \
    	68, /* /reserved-memory/image_ns@20040000 */ \
    	69, /* /reserved-memory/image_s@20000000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_reserved_memory_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_reserved_memory_REG_NUM 0
    #define DT_N_S_reserved_memory_RANGES_NUM 0
    #define DT_N_S_reserved_memory_FOREACH_RANGE(fn) 
    #define DT_N_S_reserved_memory_IRQ_NUM 0
    #define DT_N_S_reserved_memory_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_reserved_memory_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /reserved-memory/memory@20070000
     *
     * Node identifier: DT_N_S_reserved_memory_S_memory_20070000
     */
    
    /* Node's full path: */
    #define DT_N_S_reserved_memory_S_memory_20070000_PATH "/reserved-memory/memory@20070000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_reserved_memory_S_memory_20070000_FULL_NAME "memory@20070000"
    
    /* Node parent (/reserved-memory) identifier: */
    #define DT_N_S_reserved_memory_S_memory_20070000_PARENT DT_N_S_reserved_memory
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_reserved_memory_S_memory_20070000_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD(fn) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_reserved_memory_S_memory_20070000_ORD 20
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_reserved_memory_S_memory_20070000_REQUIRES_ORDS \
    	19, /* /reserved-memory */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_reserved_memory_S_memory_20070000_SUPPORTS_ORDS \
    	23, /* /ipc/ipc0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_reserved_memory_S_memory_20070000_EXISTS 1
    #define DT_N_NODELABEL_sram0_shared DT_N_S_reserved_memory_S_memory_20070000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_reserved_memory_S_memory_20070000_REG_NUM 1
    #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_ADDRESS 537329664 /* 0x20070000 */
    #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
    #define DT_N_S_reserved_memory_S_memory_20070000_RANGES_NUM 0
    #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_RANGE(fn) 
    #define DT_N_S_reserved_memory_S_memory_20070000_IRQ_NUM 0
    #define DT_N_S_reserved_memory_S_memory_20070000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_reserved_memory_S_memory_20070000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg {537329664 /* 0x20070000 */, 65536 /* 0x10000 */}
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0 537329664
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1 65536
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 0) \
    	fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 1)
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 1)
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_memory_20070000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/interrupt-controller@e000e100
     *
     * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
     *
     * Binding (compatible = arm,v8m-nvic):
     *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 21
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
    	22, /* /soc/peripheral@50000000/mbox@2a000 */ \
    	65, /* /soc/peripheral@50000000/pwm@21000 */ \
    	71, /* /soc/gpiote@4002f000 */ \
    	72, /* /soc/gpiote@5000d000 */ \
    	74, /* /soc/spu@50003000 */ \
    	78, /* /soc/crypto@50844000/crypto@50845000 */ \
    	79, /* /soc/peripheral@50000000/adc@e000 */ \
    	80, /* /soc/peripheral@50000000/clock@5000 */ \
    	81, /* /soc/peripheral@50000000/comparator@1a000 */ \
    	85, /* /soc/peripheral@50000000/egu@1b000 */ \
    	86, /* /soc/peripheral@50000000/egu@1c000 */ \
    	87, /* /soc/peripheral@50000000/egu@1d000 */ \
    	88, /* /soc/peripheral@50000000/egu@1e000 */ \
    	89, /* /soc/peripheral@50000000/egu@1f000 */ \
    	90, /* /soc/peripheral@50000000/egu@20000 */ \
    	91, /* /soc/peripheral@50000000/i2c@8000 */ \
    	92, /* /soc/peripheral@50000000/i2c@b000 */ \
    	93, /* /soc/peripheral@50000000/i2c@c000 */ \
    	94, /* /soc/peripheral@50000000/i2s@28000 */ \
    	96, /* /soc/peripheral@50000000/kmu@39000 */ \
    	98, /* /soc/peripheral@50000000/nfct@2d000 */ \
    	100, /* /soc/peripheral@50000000/pdm@26000 */ \
    	101, /* /soc/peripheral@50000000/pwm@22000 */ \
    	102, /* /soc/peripheral@50000000/pwm@23000 */ \
    	103, /* /soc/peripheral@50000000/pwm@24000 */ \
    	104, /* /soc/peripheral@50000000/qdec@33000 */ \
    	105, /* /soc/peripheral@50000000/qdec@34000 */ \
    	107, /* /soc/peripheral@50000000/regulator@37000 */ \
    	109, /* /soc/peripheral@50000000/rtc@14000 */ \
    	110, /* /soc/peripheral@50000000/rtc@15000 */ \
    	111, /* /soc/peripheral@50000000/spi@8000 */ \
    	112, /* /soc/peripheral@50000000/spi@9000 */ \
    	113, /* /soc/peripheral@50000000/spi@a000 */ \
    	114, /* /soc/peripheral@50000000/spi@c000 */ \
    	115, /* /soc/peripheral@50000000/timer@f000 */ \
    	116, /* /soc/peripheral@50000000/timer@10000 */ \
    	117, /* /soc/peripheral@50000000/timer@11000 */ \
    	118, /* /soc/peripheral@50000000/uart@8000 */ \
    	119, /* /soc/peripheral@50000000/uart@9000 */ \
    	120, /* /soc/peripheral@50000000/uart@b000 */ \
    	121, /* /soc/peripheral@50000000/uart@c000 */ \
    	122, /* /soc/peripheral@50000000/usbd@36000 */ \
    	124, /* /soc/peripheral@50000000/watchdog@18000 */ \
    	125, /* /soc/peripheral@50000000/watchdog@19000 */ \
    	135, /* /soc/peripheral@50000000/i2c@9000 */ \
    	137, /* /soc/peripheral@50000000/power@5000 */ \
    	140, /* /soc/peripheral@50000000/qspi@2b000 */ \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
    #define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
    #define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
    #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
    #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic"
    #define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0) \
    	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v8m-nvic
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/mbox@2a000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
     *
     * Binding (compatible = nordic,mbox-nrf-ipc):
     *   $ZEPHYR_BASE\dts\bindings\mbox\nordic,mbox-nrf-ipc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PATH "/soc/peripheral@50000000/mbox@2a000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME "mbox@2a000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_IDX 42
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_ORD 22
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_SUPPORTS_ORDS \
    	23, /* /ipc/ipc0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_EXISTS 1
    #define DT_N_INST_0_nordic_mbox_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_INST_0_nordic_nrf_ipc      DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_NODELABEL_mbox             DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_NODELABEL_ipc              DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq 42
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_mbox_nrf_ipc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0 "mbox-nrf-ipc"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1 "nrf-ipc"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask 65535
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask 65535
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0 42
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible {"nordic,mbox-nrf-ipc", "nordic,nrf-ipc"}
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0 "nordic,mbox-nrf-ipc"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,mbox-nrf-ipc
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_TOKEN nordic_mbox_nrf_ipc
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_MBOX_NRF_IPC
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1 "nordic,nrf-ipc"
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-ipc
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_ipc
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_IPC
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0 172032
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /ipc/ipc0
     *
     * Node identifier: DT_N_S_ipc_S_ipc0
     *
     * Binding (compatible = zephyr,ipc-openamp-static-vrings):
     *   $ZEPHYR_BASE\dts\bindings\ipc\zephyr,ipc-openamp-static-vrings.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_ipc_S_ipc0_PATH "/ipc/ipc0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_ipc_S_ipc0_FULL_NAME "ipc0"
    
    /* Node parent (/ipc) identifier: */
    #define DT_N_S_ipc_S_ipc0_PARENT DT_N_S_ipc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_ipc_S_ipc0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD(fn) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_ipc_S_ipc0_ORD 23
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_ipc_S_ipc0_REQUIRES_ORDS \
    	18, /* /ipc */ \
    	20, /* /reserved-memory/memory@20070000 */ \
    	22, /* /soc/peripheral@50000000/mbox@2a000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_ipc_S_ipc0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_ipc_S_ipc0_EXISTS 1
    #define DT_N_INST_0_zephyr_ipc_openamp_static_vrings DT_N_S_ipc_S_ipc0
    #define DT_N_NODELABEL_ipc0                          DT_N_S_ipc_S_ipc0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_ipc_S_ipc0_REG_NUM 0
    #define DT_N_S_ipc_S_ipc0_RANGES_NUM 0
    #define DT_N_S_ipc_S_ipc0_FOREACH_RANGE(fn) 
    #define DT_N_S_ipc_S_ipc0_IRQ_NUM 0
    #define DT_N_S_ipc_S_ipc0_COMPAT_MATCHES_zephyr_ipc_openamp_static_vrings 1
    #define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
    #define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0 "ipc-openamp-static-vrings"
    #define DT_N_S_ipc_S_ipc0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_ipc_S_ipc0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_ipc_S_ipc0_P_role "host"
    #define DT_N_S_ipc_S_ipc0_P_role_STRING_UNQUOTED host
    #define DT_N_S_ipc_S_ipc0_P_role_STRING_TOKEN host
    #define DT_N_S_ipc_S_ipc0_P_role_STRING_UPPER_TOKEN HOST
    #define DT_N_S_ipc_S_ipc0_P_role_ENUM_IDX 0
    #define DT_N_S_ipc_S_ipc0_P_role_ENUM_TOKEN host
    #define DT_N_S_ipc_S_ipc0_P_role_ENUM_UPPER_TOKEN HOST
    #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, role, 0) \
    	fn(DT_N_S_ipc_S_ipc0, role, 1) \
    	fn(DT_N_S_ipc_S_ipc0, role, 2) \
    	fn(DT_N_S_ipc_S_ipc0, role, 3)
    #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, role, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 3)
    #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, role, 1, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, role, 2, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, role, 3, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, role, 3, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_role_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_memory_region DT_N_S_reserved_memory_S_memory_20070000
    #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0 DT_N_S_reserved_memory_S_memory_20070000
    #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_PH DT_N_S_reserved_memory_S_memory_20070000
    #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_memory_region_LEN 1
    #define DT_N_S_ipc_S_ipc0_P_memory_region_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel 0
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_NAME "tx"
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_NAME "rx"
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel
    #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) \
    	fn(DT_N_S_ipc_S_ipc0, mboxes, 1)
    #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, mboxes, 1)
    #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_mboxes_LEN 2
    #define DT_N_S_ipc_S_ipc0_P_mboxes_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mbox_names {"tx", "rx"}
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0 "tx"
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UNQUOTED tx
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_TOKEN tx
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UPPER_TOKEN TX
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1 "rx"
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UNQUOTED rx
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_TOKEN rx
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UPPER_TOKEN RX
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) \
    	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1)
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1)
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_LEN 2
    #define DT_N_S_ipc_S_ipc0_P_mbox_names_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_status "okay"
    #define DT_N_S_ipc_S_ipc0_P_status_STRING_UNQUOTED okay
    #define DT_N_S_ipc_S_ipc0_P_status_STRING_TOKEN okay
    #define DT_N_S_ipc_S_ipc0_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_ipc_S_ipc0_P_status_ENUM_IDX 1
    #define DT_N_S_ipc_S_ipc0_P_status_ENUM_TOKEN okay
    #define DT_N_S_ipc_S_ipc0_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, status, 0) \
    	fn(DT_N_S_ipc_S_ipc0, status, 1) \
    	fn(DT_N_S_ipc_S_ipc0, status, 2) \
    	fn(DT_N_S_ipc_S_ipc0, status, 3)
    #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 3)
    #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_ipc_S_ipc0, status, 3, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_ipc_S_ipc0, status, 3, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_status_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_compatible {"zephyr,ipc-openamp-static-vrings"}
    #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0 "zephyr,ipc-openamp-static-vrings"
    #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,ipc-openamp-static-vrings
    #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_TOKEN zephyr_ipc_openamp_static_vrings
    #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_IPC_OPENAMP_STATIC_VRINGS
    #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, compatible, 0)
    #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, compatible, 0)
    #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_ipc_S_ipc0_P_compatible_LEN 1
    #define DT_N_S_ipc_S_ipc0_P_compatible_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_wakeup_source 0
    #define DT_N_S_ipc_S_ipc0_P_wakeup_source_EXISTS 1
    #define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /leds
     *
     * Node identifier: DT_N_S_leds
     *
     * Binding (compatible = gpio-leds):
     *   $ZEPHYR_BASE\dts\bindings\led\gpio-leds.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_leds_PATH "/leds"
    
    /* Node's name with unit-address: */
    #define DT_N_S_leds_FULL_NAME "leds"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_leds_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_leds_CHILD_IDX 7
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
    #define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
    #define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
    #define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
    #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
    #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
    #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
    #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_leds_ORD 24
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_leds_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_leds_SUPPORTS_ORDS \
    	25, /* /leds/led_0 */ \
    	26, /* /leds/led_1 */ \
    	27, /* /leds/led_2 */ \
    	28, /* /leds/led_3 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_leds_EXISTS 1
    #define DT_N_INST_0_gpio_leds DT_N_S_leds
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_leds_REG_NUM 0
    #define DT_N_S_leds_RANGES_NUM 0
    #define DT_N_S_leds_FOREACH_RANGE(fn) 
    #define DT_N_S_leds_IRQ_NUM 0
    #define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
    #define DT_N_S_leds_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_leds_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_leds_P_compatible {"gpio-leds"}
    #define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
    #define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
    #define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
    #define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
    #define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
    #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
    #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
    #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
    #define DT_N_S_leds_P_compatible_LEN 1
    #define DT_N_S_leds_P_compatible_EXISTS 1
    
    /*
     * Devicetree node: /leds/led_0
     *
     * Node identifier: DT_N_S_leds_S_led_0
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_leds_S_led_0_PATH "/leds/led_0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_leds_S_led_0_FULL_NAME "led_0"
    
    /* Node parent (/leds) identifier: */
    #define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_leds_S_led_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_leds_S_led_0_ORD 25
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	24, /* /leds */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_leds_S_led_0_EXISTS 1
    #define DT_N_ALIAS_led0            DT_N_S_leds_S_led_0
    #define DT_N_ALIAS_bootloader_led0 DT_N_S_leds_S_led_0
    #define DT_N_ALIAS_mcuboot_led0    DT_N_S_leds_S_led_0
    #define DT_N_NODELABEL_led0        DT_N_S_leds_S_led_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_leds_S_led_0_REG_NUM 0
    #define DT_N_S_leds_S_led_0_RANGES_NUM 0
    #define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
    #define DT_N_S_leds_S_led_0_IRQ_NUM 0
    #define DT_N_S_leds_S_led_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_leds_S_led_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 28
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
    #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
    #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_0_P_gpios_LEN 1
    #define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
    #define DT_N_S_leds_S_led_0_P_label "Led Red"
    #define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED Led Red
    #define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Led_Red
    #define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN LED_RED
    #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0) \
    	fn(DT_N_S_leds_S_led_0, label, 1) \
    	fn(DT_N_S_leds_S_led_0, label, 2) \
    	fn(DT_N_S_leds_S_led_0, label, 3) \
    	fn(DT_N_S_leds_S_led_0, label, 4) \
    	fn(DT_N_S_leds_S_led_0, label, 5) \
    	fn(DT_N_S_leds_S_led_0, label, 6)
    #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 6)
    #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__)
    #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__)
    #define DT_N_S_leds_S_led_0_P_label_EXISTS 1
    
    /*
     * Devicetree node: /leds/led_1
     *
     * Node identifier: DT_N_S_leds_S_led_1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_leds_S_led_1_PATH "/leds/led_1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_leds_S_led_1_FULL_NAME "led_1"
    
    /* Node parent (/leds) identifier: */
    #define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_leds_S_led_1_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_leds_S_led_1_ORD 26
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	24, /* /leds */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_leds_S_led_1_EXISTS 1
    #define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
    #define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_leds_S_led_1_REG_NUM 0
    #define DT_N_S_leds_S_led_1_RANGES_NUM 0
    #define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) 
    #define DT_N_S_leds_S_led_1_IRQ_NUM 0
    #define DT_N_S_leds_S_led_1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_leds_S_led_1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 29
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0)
    #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0)
    #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_1_P_gpios_LEN 1
    #define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
    #define DT_N_S_leds_S_led_1_P_label "Led Blue"
    #define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED Led Blue
    #define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Led_Blue
    #define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN LED_BLUE
    #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0) \
    	fn(DT_N_S_leds_S_led_1, label, 1) \
    	fn(DT_N_S_leds_S_led_1, label, 2) \
    	fn(DT_N_S_leds_S_led_1, label, 3) \
    	fn(DT_N_S_leds_S_led_1, label, 4) \
    	fn(DT_N_S_leds_S_led_1, label, 5) \
    	fn(DT_N_S_leds_S_led_1, label, 6) \
    	fn(DT_N_S_leds_S_led_1, label, 7)
    #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 7)
    #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_1, label, 7, __VA_ARGS__)
    #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_1, label, 7, __VA_ARGS__)
    #define DT_N_S_leds_S_led_1_P_label_EXISTS 1
    
    /*
     * Devicetree node: /leds/led_2
     *
     * Node identifier: DT_N_S_leds_S_led_2
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_leds_S_led_2_PATH "/leds/led_2"
    
    /* Node's name with unit-address: */
    #define DT_N_S_leds_S_led_2_FULL_NAME "led_2"
    
    /* Node parent (/leds) identifier: */
    #define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_leds_S_led_2_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_leds_S_led_2_ORD 27
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	24, /* /leds */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_leds_S_led_2_EXISTS 1
    #define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
    #define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_leds_S_led_2_REG_NUM 0
    #define DT_N_S_leds_S_led_2_RANGES_NUM 0
    #define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) 
    #define DT_N_S_leds_S_led_2_IRQ_NUM 0
    #define DT_N_S_leds_S_led_2_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_leds_S_led_2_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 30
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0)
    #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0)
    #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_2_P_gpios_LEN 1
    #define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
    #define DT_N_S_leds_S_led_2_P_label "Led Green"
    #define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED Led Green
    #define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Led_Green
    #define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN LED_GREEN
    #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0) \
    	fn(DT_N_S_leds_S_led_2, label, 1) \
    	fn(DT_N_S_leds_S_led_2, label, 2) \
    	fn(DT_N_S_leds_S_led_2, label, 3) \
    	fn(DT_N_S_leds_S_led_2, label, 4) \
    	fn(DT_N_S_leds_S_led_2, label, 5) \
    	fn(DT_N_S_leds_S_led_2, label, 6) \
    	fn(DT_N_S_leds_S_led_2, label, 7) \
    	fn(DT_N_S_leds_S_led_2, label, 8)
    #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 8)
    #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_2, label, 8, __VA_ARGS__)
    #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_2, label, 8, __VA_ARGS__)
    #define DT_N_S_leds_S_led_2_P_label_EXISTS 1
    
    /*
     * Devicetree node: /leds/led_3
     *
     * Node identifier: DT_N_S_leds_S_led_3
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_leds_S_led_3_PATH "/leds/led_3"
    
    /* Node's name with unit-address: */
    #define DT_N_S_leds_S_led_3_FULL_NAME "led_3"
    
    /* Node parent (/leds) identifier: */
    #define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_leds_S_led_3_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_leds_S_led_3_ORD 28
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	24, /* /leds */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_leds_S_led_3_EXISTS 1
    #define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
    #define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_leds_S_led_3_REG_NUM 0
    #define DT_N_S_leds_S_led_3_RANGES_NUM 0
    #define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) 
    #define DT_N_S_leds_S_led_3_IRQ_NUM 0
    #define DT_N_S_leds_S_led_3_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_leds_S_led_3_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 31
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 1
    #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0)
    #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0)
    #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
    #define DT_N_S_leds_S_led_3_P_gpios_LEN 1
    #define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
    #define DT_N_S_leds_S_led_3_P_label "Green LED 3"
    #define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED Green LED 3
    #define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN Green_LED_3
    #define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN GREEN_LED_3
    #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0) \
    	fn(DT_N_S_leds_S_led_3, label, 1) \
    	fn(DT_N_S_leds_S_led_3, label, 2) \
    	fn(DT_N_S_leds_S_led_3, label, 3) \
    	fn(DT_N_S_leds_S_led_3, label, 4) \
    	fn(DT_N_S_leds_S_led_3, label, 5) \
    	fn(DT_N_S_leds_S_led_3, label, 6) \
    	fn(DT_N_S_leds_S_led_3, label, 7) \
    	fn(DT_N_S_leds_S_led_3, label, 8) \
    	fn(DT_N_S_leds_S_led_3, label, 9) \
    	fn(DT_N_S_leds_S_led_3, label, 10)
    #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 10)
    #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_leds_S_led_3, label, 10, __VA_ARGS__)
    #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_leds_S_led_3, label, 10, __VA_ARGS__)
    #define DT_N_S_leds_S_led_3_P_label_EXISTS 1
    
    /*
     * Devicetree node: /nrf-gpio-forwarder
     *
     * Node identifier: DT_N_S_nrf_gpio_forwarder
     *
     * Binding (compatible = nordic,nrf-gpio-forwarder):
     *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio-forwarder.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_nrf_gpio_forwarder_PATH "/nrf-gpio-forwarder"
    
    /* Node's name with unit-address: */
    #define DT_N_S_nrf_gpio_forwarder_FULL_NAME "nrf-gpio-forwarder"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_nrf_gpio_forwarder_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_nrf_gpio_forwarder_CHILD_IDX 12
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD(fn) fn(DT_N_S_nrf_gpio_forwarder_S_uart)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder_S_uart)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_nrf_gpio_forwarder_S_uart)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder_S_uart)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_nrf_gpio_forwarder_ORD 29
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_nrf_gpio_forwarder_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_nrf_gpio_forwarder_SUPPORTS_ORDS \
    	31, /* /nrf-gpio-forwarder/uart */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_nrf_gpio_forwarder_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_gpio_forwarder DT_N_S_nrf_gpio_forwarder
    #define DT_N_NODELABEL_gpio_fwd               DT_N_S_nrf_gpio_forwarder
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_nrf_gpio_forwarder_REG_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_RANGES_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_FOREACH_RANGE(fn) 
    #define DT_N_S_nrf_gpio_forwarder_IRQ_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_COMPAT_MATCHES_nordic_nrf_gpio_forwarder 1
    #define DT_N_S_nrf_gpio_forwarder_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_nrf_gpio_forwarder_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_COMPAT_MODEL_IDX_0 "nrf-gpio-forwarder"
    #define DT_N_S_nrf_gpio_forwarder_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_nrf_gpio_forwarder_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_nrf_gpio_forwarder_P_status "okay"
    #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_UNQUOTED okay
    #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_TOKEN okay
    #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_nrf_gpio_forwarder_P_status_ENUM_IDX 1
    #define DT_N_S_nrf_gpio_forwarder_P_status_ENUM_TOKEN okay
    #define DT_N_S_nrf_gpio_forwarder_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_nrf_gpio_forwarder, status, 0) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 1) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 2) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 3)
    #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 3)
    #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 3, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder, status, 3, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_P_status_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_P_compatible {"nordic,nrf-gpio-forwarder"}
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0 "nordic,nrf-gpio-forwarder"
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio-forwarder
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio_forwarder
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO_FORWARDER
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0)
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0)
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_LEN 1
    #define DT_N_S_nrf_gpio_forwarder_P_compatible_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_P_wakeup_source 0
    #define DT_N_S_nrf_gpio_forwarder_P_wakeup_source_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_nrf_gpio_forwarder_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/gpio@842800
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
     *
     * Binding (compatible = nordic,nrf-gpio):
     *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PATH "/soc/peripheral@50000000/gpio@842800"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME "gpio@842800"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_IDX 54
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_ORD 30
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_SUPPORTS_ORDS \
    	31, /* /nrf-gpio-forwarder/uart */ \
    	113, /* /soc/peripheral@50000000/spi@a000 */ \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    #define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_ADDRESS 1350838272 /* 0x50842800 */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MATCHES_nordic_nrf_gpio 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0 "nrf-gpio"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg {8660992 /* 0x842800 */, 768 /* 0x300 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0 8660992
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1 768
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios 16
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible {"nordic,nrf-gpio"}
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0 "nordic,nrf-gpio"
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /nrf-gpio-forwarder/uart
     *
     * Node identifier: DT_N_S_nrf_gpio_forwarder_S_uart
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_PATH "/nrf-gpio-forwarder/uart"
    
    /* Node's name with unit-address: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FULL_NAME "uart"
    
    /* Node parent (/nrf-gpio-forwarder) identifier: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_PARENT DT_N_S_nrf_gpio_forwarder
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD(fn) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_ORD 31
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_REQUIRES_ORDS \
    	9, /* /soc/peripheral@50000000/gpio@842500 */ \
    	29, /* /nrf-gpio-forwarder */ \
    	30, /* /soc/peripheral@50000000/gpio@842800 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_REG_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_RANGES_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_FOREACH_RANGE(fn) 
    #define DT_N_S_nrf_gpio_forwarder_S_uart_IRQ_NUM 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_VAL_pin 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_VAL_flags 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_VAL_pin 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_VAL_pin_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_VAL_flags 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_1_VAL_flags_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_VAL_pin 11
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_VAL_pin_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_VAL_flags 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_2_VAL_flags_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_VAL_pin 10
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_VAL_pin_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_VAL_flags 0
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_IDX_3_VAL_flags_EXISTS 1
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 0) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 1) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 2) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 3)
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 3)
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 0, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 1, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 2, __VA_ARGS__) \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 3, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_nrf_gpio_forwarder_S_uart, gpios, 3, __VA_ARGS__)
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_LEN 4
    #define DT_N_S_nrf_gpio_forwarder_S_uart_P_gpios_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller
     *
     * Node identifier: DT_N_S_pin_controller
     *
     * Binding (compatible = nordic,nrf-pinctrl):
     *   $ZEPHYR_BASE\dts\bindings\pinctrl\nordic,nrf-pinctrl.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_PATH "/pin-controller"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_FULL_NAME "pin-controller"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_pin_controller_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)
    #define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep)
    #define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
    #define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
    #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)
    #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep)
    #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
    #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_ORD 32
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_SUPPORTS_ORDS \
    	33, /* /pin-controller/i2c1_default */ \
    	35, /* /pin-controller/i2c1_sleep */ \
    	37, /* /pin-controller/pwm0_default */ \
    	39, /* /pin-controller/pwm0_sleep */ \
    	41, /* /pin-controller/qspi_default */ \
    	43, /* /pin-controller/qspi_sleep */ \
    	46, /* /pin-controller/spi2_default */ \
    	48, /* /pin-controller/spi2_sleep */ \
    	50, /* /pin-controller/spi4_default */ \
    	52, /* /pin-controller/spi4_sleep */ \
    	54, /* /pin-controller/uart0_default */ \
    	57, /* /pin-controller/uart0_sleep */ \
    	59, /* /pin-controller/uart1_default */ \
    	62, /* /pin-controller/uart1_sleep */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller
    #define DT_N_NODELABEL_pinctrl         DT_N_S_pin_controller
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_REG_NUM 0
    #define DT_N_S_pin_controller_RANGES_NUM 0
    #define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_IRQ_NUM 0
    #define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1
    #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl"
    #define DT_N_S_pin_controller_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"}
    #define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl"
    #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl
    #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl
    #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL
    #define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
    #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
    #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_P_compatible_LEN 1
    #define DT_N_S_pin_controller_P_compatible_EXISTS 1
    #define DT_N_S_pin_controller_P_wakeup_source 0
    #define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1
    #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/i2c1_default
     *
     * Node identifier: DT_N_S_pin_controller_S_i2c1_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_i2c1_default_PATH "/pin-controller/i2c1_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME "i2c1_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_i2c1_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_i2c1_default_ORD 33
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS \
    	34, /* /pin-controller/i2c1_default/group1 */ \
    	135, /* /soc/peripheral@50000000/i2c@9000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_i2c1_default_EXISTS 1
    #define DT_N_NODELABEL_i2c1_default DT_N_S_pin_controller_S_i2c1_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_i2c1_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/i2c1_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_i2c1_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH "/pin-controller/i2c1_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/i2c1_default) identifier: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD 34
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS \
    	33, /* /pin-controller/i2c1_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels {786437 /* 0xc0005 */, 720900 /* 0xb0004 */}
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0 786437
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1 720900
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN 2
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode 6
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/i2c1_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_PATH "/pin-controller/i2c1_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME "i2c1_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_ORD 35
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS \
    	36, /* /pin-controller/i2c1_sleep/group1 */ \
    	135, /* /soc/peripheral@50000000/i2c@9000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_EXISTS 1
    #define DT_N_NODELABEL_i2c1_sleep DT_N_S_pin_controller_S_i2c1_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/i2c1_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH "/pin-controller/i2c1_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/i2c1_sleep) identifier: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD 36
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS \
    	35, /* /pin-controller/i2c1_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels {786437 /* 0xc0005 */, 720900 /* 0xb0004 */}
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0 786437
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1 720900
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN 2
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/pwm0_default
     *
     * Node identifier: DT_N_S_pin_controller_S_pwm0_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_pwm0_default_PATH "/pin-controller/pwm0_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_pwm0_default_FULL_NAME "pwm0_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_pwm0_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_pwm0_default_CHILD_IDX 4
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_pwm0_default_ORD 37
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_pwm0_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_pwm0_default_SUPPORTS_ORDS \
    	38, /* /pin-controller/pwm0_default/group1 */ \
    	65, /* /soc/peripheral@50000000/pwm@21000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_pwm0_default_EXISTS 1
    #define DT_N_NODELABEL_pwm0_default DT_N_S_pin_controller_S_pwm0_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_pwm0_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_pwm0_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_pwm0_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/pwm0_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_pwm0_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PATH "/pin-controller/pwm0_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/pwm0_default) identifier: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_ORD 38
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_REQUIRES_ORDS \
    	37, /* /pin-controller/pwm0_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels {1441820 /* 0x16001c */}
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0 1441820
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_LEN 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/pwm0_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_PATH "/pin-controller/pwm0_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME "pwm0_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_IDX 5
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_ORD 39
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_SUPPORTS_ORDS \
    	40, /* /pin-controller/pwm0_sleep/group1 */ \
    	65, /* /soc/peripheral@50000000/pwm@21000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_EXISTS 1
    #define DT_N_NODELABEL_pwm0_sleep DT_N_S_pin_controller_S_pwm0_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/pwm0_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PATH "/pin-controller/pwm0_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/pwm0_sleep) identifier: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD 40
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REQUIRES_ORDS \
    	39, /* /pin-controller/pwm0_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels {1441820 /* 0x16001c */}
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0 1441820
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_LEN 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/qspi_default
     *
     * Node identifier: DT_N_S_pin_controller_S_qspi_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_qspi_default_PATH "/pin-controller/qspi_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_qspi_default_FULL_NAME "qspi_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_qspi_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_qspi_default_CHILD_IDX 6
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_qspi_default_ORD 41
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_qspi_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_qspi_default_SUPPORTS_ORDS \
    	42, /* /pin-controller/qspi_default/group1 */ \
    	140, /* /soc/peripheral@50000000/qspi@2b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_qspi_default_EXISTS 1
    #define DT_N_NODELABEL_qspi_default DT_N_S_pin_controller_S_qspi_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_qspi_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_qspi_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_qspi_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/qspi_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_qspi_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_PATH "/pin-controller/qspi_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/qspi_default) identifier: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_PARENT DT_N_S_pin_controller_S_qspi_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_ORD 42
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_REQUIRES_ORDS \
    	41, /* /pin-controller/qspi_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels {1900561 /* 0x1d0011 */, 2031629 /* 0x1f000d */, 2097166 /* 0x20000e */, 2162703 /* 0x21000f */, 2228240 /* 0x220010 */, 1966098 /* 0x1e0012 */}
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0 1900561
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1 2031629
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2 2097166
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3 2162703
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4 2228240
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5 1966098
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5)
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5)
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_LEN 6
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode 3
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/qspi_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_qspi_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_qspi_sleep_PATH "/pin-controller/qspi_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME "qspi_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_qspi_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_qspi_sleep_CHILD_IDX 7
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_qspi_sleep_ORD 43
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_qspi_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_qspi_sleep_SUPPORTS_ORDS \
    	44, /* /pin-controller/qspi_sleep/group1 */ \
    	45, /* /pin-controller/qspi_sleep/group2 */ \
    	140, /* /soc/peripheral@50000000/qspi@2b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_qspi_sleep_EXISTS 1
    #define DT_N_NODELABEL_qspi_sleep DT_N_S_pin_controller_S_qspi_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_qspi_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_qspi_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/qspi_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PATH "/pin-controller/qspi_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/qspi_sleep) identifier: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PARENT DT_N_S_pin_controller_S_qspi_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_ORD 44
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REQUIRES_ORDS \
    	43, /* /pin-controller/qspi_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels {1900561 /* 0x1d0011 */, 2031629 /* 0x1f000d */, 2097166 /* 0x20000e */, 2162703 /* 0x21000f */, 2228240 /* 0x220010 */}
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0 1900561
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1 2031629
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2 2097166
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3 2162703
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4 2228240
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_LEN 5
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/qspi_sleep/group2
     *
     * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group2
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PATH "/pin-controller/qspi_sleep/group2"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME "group2"
    
    /* Node parent (/pin-controller/qspi_sleep) identifier: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PARENT DT_N_S_pin_controller_S_qspi_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_ORD 45
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REQUIRES_ORDS \
    	43, /* /pin-controller/qspi_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REG_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels {1966098 /* 0x1e0012 */}
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0 1966098
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_LEN 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/spi2_default
     *
     * Node identifier: DT_N_S_pin_controller_S_spi2_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi2_default_PATH "/pin-controller/spi2_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi2_default_FULL_NAME "spi2_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_spi2_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi2_default_CHILD_IDX 12
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi2_default_ORD 46
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi2_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi2_default_SUPPORTS_ORDS \
    	47, /* /pin-controller/spi2_default/group1 */ \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi2_default_EXISTS 1
    #define DT_N_NODELABEL_spi2_default DT_N_S_pin_controller_S_spi2_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi2_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi2_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi2_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/spi2_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_spi2_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_PATH "/pin-controller/spi2_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/spi2_default) identifier: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_PARENT DT_N_S_pin_controller_S_spi2_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_ORD 47
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_REQUIRES_ORDS \
    	46, /* /pin-controller/spi2_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels {262188 /* 0x4002c */, 393262 /* 0x6002e */, 327725 /* 0x5002d */}
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0 262188
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1 393262
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2 327725
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_LEN 3
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/spi2_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_spi2_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi2_sleep_PATH "/pin-controller/spi2_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi2_sleep_FULL_NAME "spi2_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_spi2_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi2_sleep_CHILD_IDX 13
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi2_sleep_ORD 48
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi2_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi2_sleep_SUPPORTS_ORDS \
    	49, /* /pin-controller/spi2_sleep/group1 */ \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi2_sleep_EXISTS 1
    #define DT_N_NODELABEL_spi2_sleep DT_N_S_pin_controller_S_spi2_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi2_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi2_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi2_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/spi2_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_spi2_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PATH "/pin-controller/spi2_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/spi2_sleep) identifier: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi2_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD 49
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REQUIRES_ORDS \
    	48, /* /pin-controller/spi2_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels {262188 /* 0x4002c */, 393262 /* 0x6002e */, 327725 /* 0x5002d */}
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0 262188
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1 393262
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2 327725
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_LEN 3
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/spi4_default
     *
     * Node identifier: DT_N_S_pin_controller_S_spi4_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi4_default_PATH "/pin-controller/spi4_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi4_default_FULL_NAME "spi4_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_spi4_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi4_default_CHILD_IDX 10
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi4_default_ORD 50
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi4_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi4_default_SUPPORTS_ORDS \
    	51, /* /pin-controller/spi4_default/group1 */ \
    	113, /* /soc/peripheral@50000000/spi@a000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi4_default_EXISTS 1
    #define DT_N_NODELABEL_spi4_default DT_N_S_pin_controller_S_spi4_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi4_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi4_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi4_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/spi4_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_spi4_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_PATH "/pin-controller/spi4_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/spi4_default) identifier: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_PARENT DT_N_S_pin_controller_S_spi4_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_ORD 51
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_REQUIRES_ORDS \
    	50, /* /pin-controller/spi4_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels {262184 /* 0x40028 */, 393258 /* 0x6002a */, 327721 /* 0x50029 */}
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0 262184
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1 393258
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2 327721
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_LEN 3
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/spi4_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_spi4_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi4_sleep_PATH "/pin-controller/spi4_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME "spi4_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_spi4_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi4_sleep_CHILD_IDX 11
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi4_sleep_ORD 52
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi4_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi4_sleep_SUPPORTS_ORDS \
    	53, /* /pin-controller/spi4_sleep/group1 */ \
    	113, /* /soc/peripheral@50000000/spi@a000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi4_sleep_EXISTS 1
    #define DT_N_NODELABEL_spi4_sleep DT_N_S_pin_controller_S_spi4_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi4_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi4_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi4_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/spi4_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_spi4_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PATH "/pin-controller/spi4_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/spi4_sleep) identifier: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi4_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_ORD 53
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REQUIRES_ORDS \
    	52, /* /pin-controller/spi4_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels {262184 /* 0x40028 */, 393258 /* 0x6002a */, 327721 /* 0x50029 */}
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0 262184
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1 393258
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2 327721
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2)
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_LEN 3
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart0_default
     *
     * Node identifier: DT_N_S_pin_controller_S_uart0_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart0_default_ORD 54
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \
    	55, /* /pin-controller/uart0_default/group1 */ \
    	56, /* /pin-controller/uart0_default/group2 */ \
    	118, /* /soc/peripheral@50000000/uart@8000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart0_default_EXISTS 1
    #define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/uart0_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/uart0_default) identifier: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 55
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \
    	54, /* /pin-controller/uart0_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels {20 /* 0x14 */, 131091 /* 0x20013 */}
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0 20
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1 131091
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN 2
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart0_default/group2
     *
     * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group2
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH "/pin-controller/uart0_default/group2"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME "group2"
    
    /* Node parent (/pin-controller/uart0_default) identifier: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT DT_N_S_pin_controller_S_uart0_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD 56
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS \
    	54, /* /pin-controller/uart0_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels {65558 /* 0x10016 */, 196629 /* 0x30015 */}
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0 65558
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1 196629
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1)
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1)
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN 2
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart0_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_uart0_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart0_sleep_PATH "/pin-controller/uart0_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME "uart0_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_uart0_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart0_sleep_ORD 57
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS \
    	58, /* /pin-controller/uart0_sleep/group1 */ \
    	118, /* /soc/peripheral@50000000/uart@8000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart0_sleep_EXISTS 1
    #define DT_N_NODELABEL_uart0_sleep DT_N_S_pin_controller_S_uart0_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/uart0_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_uart0_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH "/pin-controller/uart0_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/uart0_sleep) identifier: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart0_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD 58
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS \
    	57, /* /pin-controller/uart0_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels {20 /* 0x14 */, 65558 /* 0x10016 */, 131091 /* 0x20013 */, 196629 /* 0x30015 */}
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0 20
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1 65558
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2 131091
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3 196629
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3)
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3)
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN 4
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart1_default
     *
     * Node identifier: DT_N_S_pin_controller_S_uart1_default
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart1_default_PATH "/pin-controller/uart1_default"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME "uart1_default"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_uart1_default_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart1_default_CHILD_IDX 8
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart1_default_ORD 59
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart1_default_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart1_default_SUPPORTS_ORDS \
    	60, /* /pin-controller/uart1_default/group1 */ \
    	61, /* /pin-controller/uart1_default/group2 */ \
    	119, /* /soc/peripheral@50000000/uart@9000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart1_default_EXISTS 1
    #define DT_N_NODELABEL_uart1_default DT_N_S_pin_controller_S_uart1_default
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart1_default_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart1_default_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/uart1_default/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_PATH "/pin-controller/uart1_default/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/uart1_default) identifier: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_PARENT DT_N_S_pin_controller_S_uart1_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD 60
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_REQUIRES_ORDS \
    	59, /* /pin-controller/uart1_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels {33 /* 0x21 */}
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0 33
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0)
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_LEN 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart1_default/group2
     *
     * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group2
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_PATH "/pin-controller/uart1_default/group2"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME "group2"
    
    /* Node parent (/pin-controller/uart1_default) identifier: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_PARENT DT_N_S_pin_controller_S_uart1_default
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD 61
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_REQUIRES_ORDS \
    	59, /* /pin-controller/uart1_default */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels {65568 /* 0x10020 */}
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0 65568
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0)
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0)
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_LEN 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable 0
    #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pin-controller/uart1_sleep
     *
     * Node identifier: DT_N_S_pin_controller_S_uart1_sleep
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart1_sleep_PATH "/pin-controller/uart1_sleep"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME "uart1_sleep"
    
    /* Node parent (/pin-controller) identifier: */
    #define DT_N_S_pin_controller_S_uart1_sleep_PARENT DT_N_S_pin_controller
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_IDX 9
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart1_sleep_ORD 62
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart1_sleep_REQUIRES_ORDS \
    	32, /* /pin-controller */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart1_sleep_SUPPORTS_ORDS \
    	63, /* /pin-controller/uart1_sleep/group1 */ \
    	119, /* /soc/peripheral@50000000/uart@9000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart1_sleep_EXISTS 1
    #define DT_N_NODELABEL_uart1_sleep DT_N_S_pin_controller_S_uart1_sleep
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart1_sleep_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart1_sleep_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart1_sleep_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /pin-controller/uart1_sleep/group1
     *
     * Node identifier: DT_N_S_pin_controller_S_uart1_sleep_S_group1
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PATH "/pin-controller/uart1_sleep/group1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME "group1"
    
    /* Node parent (/pin-controller/uart1_sleep) identifier: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart1_sleep
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD(fn) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD 63
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REQUIRES_ORDS \
    	62, /* /pin-controller/uart1_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_EXISTS 1
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REG_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_RANGES_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_RANGE(fn) 
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_NUM 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels {33 /* 0x21 */, 65568 /* 0x10020 */}
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0 33
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1 65568
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) \
    	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1)
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) \
    	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__)
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_LEN 2
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down 0
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down_EXISTS 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable 1
    #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable_EXISTS 1
    
    /*
     * Devicetree node: /pwmleds
     *
     * Node identifier: DT_N_S_pwmleds
     *
     * Binding (compatible = pwm-leds):
     *   $ZEPHYR_BASE\dts\bindings\led\pwm-leds.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pwmleds_PATH "/pwmleds"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pwmleds_FULL_NAME "pwmleds"
    
    /* Node parent (/) identifier: */
    #define DT_N_S_pwmleds_PARENT DT_N
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pwmleds_CHILD_IDX 8
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_pwm_led_0)
    #define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0)
    #define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
    #define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
    #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_pwm_led_0)
    #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0)
    #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
    #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pwmleds_ORD 64
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pwmleds_REQUIRES_ORDS \
    	0, /* / */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pwmleds_SUPPORTS_ORDS \
    	66, /* /pwmleds/pwm_led_0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pwmleds_EXISTS 1
    #define DT_N_INST_0_pwm_leds DT_N_S_pwmleds
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pwmleds_REG_NUM 0
    #define DT_N_S_pwmleds_RANGES_NUM 0
    #define DT_N_S_pwmleds_FOREACH_RANGE(fn) 
    #define DT_N_S_pwmleds_IRQ_NUM 0
    #define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1
    #define DT_N_S_pwmleds_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pwmleds_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pwmleds_P_compatible {"pwm-leds"}
    #define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds"
    #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds
    #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds
    #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS
    #define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0)
    #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0)
    #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
    #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
    #define DT_N_S_pwmleds_P_compatible_LEN 1
    #define DT_N_S_pwmleds_P_compatible_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/pwm@21000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
     *
     * Binding (compatible = nordic,nrf-pwm):
     *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PATH "/soc/peripheral@50000000/pwm@21000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME "pwm@21000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_IDX 36
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD 65
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	37, /* /pin-controller/pwm0_default */ \
    	39, /* /pin-controller/pwm0_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_SUPPORTS_ORDS \
    	66, /* /pwmleds/pwm_led_0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
    #define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0 "nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm0_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /pwmleds/pwm_led_0
     *
     * Node identifier: DT_N_S_pwmleds_S_pwm_led_0
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_pwmleds_S_pwm_led_0_PATH "/pwmleds/pwm_led_0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME "pwm_led_0"
    
    /* Node parent (/pwmleds) identifier: */
    #define DT_N_S_pwmleds_S_pwm_led_0_PARENT DT_N_S_pwmleds
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD(fn) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_pwmleds_S_pwm_led_0_ORD 66
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_pwmleds_S_pwm_led_0_REQUIRES_ORDS \
    	64, /* /pwmleds */ \
    	65, /* /soc/peripheral@50000000/pwm@21000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_pwmleds_S_pwm_led_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_pwmleds_S_pwm_led_0_EXISTS 1
    #define DT_N_ALIAS_pwm_led0     DT_N_S_pwmleds_S_pwm_led_0
    #define DT_N_NODELABEL_pwm_led0 DT_N_S_pwmleds_S_pwm_led_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_pwmleds_S_pwm_led_0_REG_NUM 0
    #define DT_N_S_pwmleds_S_pwm_led_0_RANGES_NUM 0
    #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_RANGE(fn) 
    #define DT_N_S_pwmleds_S_pwm_led_0_IRQ_NUM 0
    #define DT_N_S_pwmleds_S_pwm_led_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_pwmleds_S_pwm_led_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_EXISTS 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel 0
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel_EXISTS 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period 20000000
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period_EXISTS 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0)
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0)
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__)
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__)
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_LEN 1
    #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_EXISTS 1
    
    /*
     * Devicetree node: /reserved-memory/image@20000000
     *
     * Node identifier: DT_N_S_reserved_memory_S_image_20000000
     */
    
    /* Node's full path: */
    #define DT_N_S_reserved_memory_S_image_20000000_PATH "/reserved-memory/image@20000000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME "image@20000000"
    
    /* Node parent (/reserved-memory) identifier: */
    #define DT_N_S_reserved_memory_S_image_20000000_PARENT DT_N_S_reserved_memory
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_reserved_memory_S_image_20000000_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD(fn) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_reserved_memory_S_image_20000000_ORD 67
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_reserved_memory_S_image_20000000_REQUIRES_ORDS \
    	19, /* /reserved-memory */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_reserved_memory_S_image_20000000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_reserved_memory_S_image_20000000_EXISTS 1
    #define DT_N_NODELABEL_sram0_image DT_N_S_reserved_memory_S_image_20000000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_reserved_memory_S_image_20000000_REG_NUM 1
    #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
    #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */
    #define DT_N_S_reserved_memory_S_image_20000000_RANGES_NUM 0
    #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_RANGE(fn) 
    #define DT_N_S_reserved_memory_S_image_20000000_IRQ_NUM 0
    #define DT_N_S_reserved_memory_S_image_20000000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_reserved_memory_S_image_20000000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg {536870912 /* 0x20000000 */, 458752 /* 0x70000 */}
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0 536870912
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1 458752
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_20000000, reg, 0) \
    	fn(DT_N_S_reserved_memory_S_image_20000000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_20000000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_reserved_memory_S_image_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_20000000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /reserved-memory/image_ns@20040000
     *
     * Node identifier: DT_N_S_reserved_memory_S_image_ns_20040000
     */
    
    /* Node's full path: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_PATH "/reserved-memory/image_ns@20040000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME "image_ns@20040000"
    
    /* Node parent (/reserved-memory) identifier: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_PARENT DT_N_S_reserved_memory
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD(fn) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_ORD 68
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_REQUIRES_ORDS \
    	19, /* /reserved-memory */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_EXISTS 1
    #define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20040000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_NUM 1
    #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_ADDRESS 537133056 /* 0x20040000 */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_RANGES_NUM 0
    #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_RANGE(fn) 
    #define DT_N_S_reserved_memory_S_image_ns_20040000_IRQ_NUM 0
    #define DT_N_S_reserved_memory_S_image_ns_20040000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg {537133056 /* 0x20040000 */, 196608 /* 0x30000 */}
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0 537133056
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1 196608
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 0) \
    	fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_ns_20040000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /reserved-memory/image_s@20000000
     *
     * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000
     */
    
    /* Node's full path: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME "image_s@20000000"
    
    /* Node parent (/reserved-memory) identifier: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_ORD 69
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \
    	19, /* /reserved-memory */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1
    #define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1
    #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
    #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
    #define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM 0
    #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn) 
    #define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0
    #define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 262144
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0) \
    	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1)
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/ficr@ff0000
     *
     * Node identifier: DT_N_S_soc_S_ficr_ff0000
     *
     * Binding (compatible = nordic,nrf-ficr):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ficr.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_ficr_ff0000_PATH "/soc/ficr@ff0000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME "ficr@ff0000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_ficr_ff0000_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_ficr_ff0000_ORD 70
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_ficr_ff0000_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_ficr_ff0000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_ficr_ff0000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000
    #define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_ff0000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1
    #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */
    #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_ficr_ff0000_RANGES_NUM 0
    #define DT_N_S_soc_S_ficr_ff0000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0
    #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1
    #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0 "nrf-ficr"
    #define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_ficr_ff0000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0) \
    	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1)
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1)
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_status "okay"
    #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 1) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 2) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 3)
    #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 3)
    #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_ficr_ff0000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"}
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr"
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1
    #define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source 0
    #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/gpiote@4002f000
     *
     * Node identifier: DT_N_S_soc_S_gpiote_4002f000
     *
     * Binding (compatible = nordic,nrf-gpiote):
     *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_gpiote_4002f000_PATH "/soc/gpiote@4002f000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME "gpiote@4002f000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_gpiote_4002f000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_gpiote_4002f000_CHILD_IDX 9
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_gpiote_4002f000_ORD 71
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_gpiote_4002f000_REQUIRES_ORDS \
    	7, /* /soc */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_gpiote_4002f000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_gpiote_4002f000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_4002f000
    #define DT_N_NODELABEL_gpiote1        DT_N_S_soc_S_gpiote_4002f000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_gpiote_4002f000_REG_NUM 1
    #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_ADDRESS 1073934336 /* 0x4002f000 */
    #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_gpiote_4002f000_RANGES_NUM 0
    #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_NUM 1
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq 47
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority 5
    #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MATCHES_nordic_nrf_gpiote 1
    #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
    #define DT_N_S_soc_S_gpiote_4002f000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_gpiote_4002f000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg {1073934336 /* 0x4002f000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0 1073934336
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, reg, 0) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, reg, 1)
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, reg, 1)
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts {47 /* 0x2f */, 5 /* 0x5 */}
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0 47
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1 5
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 0) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 1)
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 1)
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_status "disabled"
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 1) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 2) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 3) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 4) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 5) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 6) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 7)
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 7)
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_4002f000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_status_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible {"nordic,nrf-gpiote"}
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0 "nordic,nrf-gpiote"
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0)
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0)
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_LEN 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source 0
    #define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/gpiote@5000d000
     *
     * Node identifier: DT_N_S_soc_S_gpiote_5000d000
     *
     * Binding (compatible = nordic,nrf-gpiote):
     *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_gpiote_5000d000_PATH "/soc/gpiote@5000d000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME "gpiote@5000d000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_gpiote_5000d000_CHILD_IDX 7
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_gpiote_5000d000_ORD 72
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_gpiote_5000d000_REQUIRES_ORDS \
    	7, /* /soc */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_gpiote_5000d000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000
    #define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_5000d000
    #define DT_N_NODELABEL_gpiote0        DT_N_S_soc_S_gpiote_5000d000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1
    #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */
    #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_gpiote_5000d000_RANGES_NUM 0
    #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5
    #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1
    #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
    #define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_gpiote_5000d000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1)
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1)
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */}
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1)
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1)
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_status "okay"
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3)
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3)
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"}
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote"
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source 0
    #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/memory@20000000
     *
     * Node identifier: DT_N_S_soc_S_memory_20000000
     *
     * Binding (compatible = mmio-sram):
     *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_memory_20000000_CHILD_IDX 4
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_memory_20000000_ORD 73
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_memory_20000000_EXISTS 1
    #define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
    #define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_memory_20000000_REG_NUM 1
    #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
    #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */
    #define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0
    #define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
    #define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
    #define DT_N_S_soc_S_memory_20000000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 524288 /* 0x80000 */}
    #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
    #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 524288
    #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, reg, 0) \
    	fn(DT_N_S_soc_S_memory_20000000, reg, 1)
    #define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_memory_20000000, reg, 1)
    #define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_memory_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_memory_20000000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
    #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
    #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
    #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
    #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
    #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
    #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
    #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
    #define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0
    #define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/spu@50003000
     *
     * Node identifier: DT_N_S_soc_S_spu_50003000
     *
     * Binding (compatible = nordic,nrf-spu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-spu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_spu_50003000_PATH "/soc/spu@50003000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_spu_50003000_FULL_NAME "spu@50003000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_spu_50003000_CHILD_IDX 6
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_spu_50003000_ORD 74
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_spu_50003000_REQUIRES_ORDS \
    	7, /* /soc */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_spu_50003000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_spu_50003000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000
    #define DT_N_NODELABEL_spu         DT_N_S_soc_S_spu_50003000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_spu_50003000_REG_NUM 1
    #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */
    #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_spu_50003000_RANGES_NUM 0
    #define DT_N_S_soc_S_spu_50003000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1
    #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0 "nrf-spu"
    #define DT_N_S_soc_S_spu_50003000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_spu_50003000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568
    #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, reg, 0) \
    	fn(DT_N_S_soc_S_spu_50003000, reg, 1)
    #define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, reg, 1)
    #define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_spu_50003000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0) \
    	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1)
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1)
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_status "okay"
    #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_spu_50003000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_spu_50003000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, status, 0) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 1) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 2) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 3)
    #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 3)
    #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_spu_50003000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_spu_50003000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"}
    #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu"
    #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spu
    #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spu
    #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPU
    #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
    #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
    #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1
    #define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_wakeup_source 0
    #define DT_N_S_soc_S_spu_50003000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/timer@e000e010
     *
     * Node identifier: DT_N_S_soc_S_timer_e000e010
     *
     * Binding (compatible = arm,armv8m-systick):
     *   $ZEPHYR_BASE\dts\bindings\timer\arm,armv8m-systick.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_timer_e000e010_ORD 75
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_timer_e000e010_EXISTS 1
    #define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
    #define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
    #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
    #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
    #define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
    #define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
    #define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
    #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick"
    #define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
    #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
    #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
    #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, reg, 0) \
    	fn(DT_N_S_soc_S_timer_e000e010, reg, 1)
    #define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, reg, 1)
    #define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
    #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 1) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 2) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 3) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 4) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 5) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 6) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 7)
    #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 7)
    #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_timer_e000e010, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-systick
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
    #define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
    #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/uicr@ff8000
     *
     * Node identifier: DT_N_S_soc_S_uicr_ff8000
     *
     * Binding (compatible = nordic,nrf-uicr):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-uicr.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_uicr_ff8000_PATH "/soc/uicr@ff8000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME "uicr@ff8000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_uicr_ff8000_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_uicr_ff8000_ORD 76
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_uicr_ff8000_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_uicr_ff8000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_uicr_ff8000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000
    #define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_ff8000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1
    #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */
    #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_uicr_ff8000_RANGES_NUM 0
    #define DT_N_S_soc_S_uicr_ff8000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0
    #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1
    #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0 "nrf-uicr"
    #define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_uicr_ff8000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0) \
    	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1)
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1)
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_status "okay"
    #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 1) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 2) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 3)
    #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 3)
    #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_uicr_ff8000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"}
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr"
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uicr
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1
    #define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source 0
    #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/crypto@50844000
     *
     * Node identifier: DT_N_S_soc_S_crypto_50844000
     *
     * Binding (compatible = nordic,nrf-cc312):
     *   $ZEPHYR_BASE\dts\bindings\crypto\nordic,nrf-cc312.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_crypto_50844000_PATH "/soc/crypto@50844000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_crypto_50844000_FULL_NAME "crypto@50844000"
    
    /* Node parent (/soc) identifier: */
    #define DT_N_S_soc_S_crypto_50844000_PARENT DT_N_S_soc
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_crypto_50844000_CHILD_IDX 8
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_crypto_50844000_ORD 77
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_crypto_50844000_REQUIRES_ORDS \
    	7, /* /soc */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_crypto_50844000_SUPPORTS_ORDS \
    	78, /* /soc/crypto@50844000/crypto@50845000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_crypto_50844000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_cc312 DT_N_S_soc_S_crypto_50844000
    #define DT_N_NODELABEL_cryptocell    DT_N_S_soc_S_crypto_50844000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_crypto_50844000_REG_NUM 1
    #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS 1350844416 /* 0x50844000 */
    #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_crypto_50844000_RANGES_NUM 0
    #define DT_N_S_soc_S_crypto_50844000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_crypto_50844000_IRQ_NUM 0
    #define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_nordic_nrf_cc312 1
    #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0 "nrf-cc312"
    #define DT_N_S_soc_S_crypto_50844000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_crypto_50844000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_crypto_50844000_P_reg {1350844416 /* 0x50844000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0 1350844416
    #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, reg, 0) \
    	fn(DT_N_S_soc_S_crypto_50844000, reg, 1)
    #define DT_N_S_soc_S_crypto_50844000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, reg, 1)
    #define DT_N_S_soc_S_crypto_50844000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_status "okay"
    #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, status, 0) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 1) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 2) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 3)
    #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 3)
    #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_status_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_compatible {"nordic,nrf-cc312"}
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0 "nordic,nrf-cc312"
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-cc312
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_cc312
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CC312
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0)
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0)
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_LEN 1
    #define DT_N_S_soc_S_crypto_50844000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_wakeup_source 0
    #define DT_N_S_soc_S_crypto_50844000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/crypto@50844000/crypto@50845000
     *
     * Node identifier: DT_N_S_soc_S_crypto_50844000_S_crypto_50845000
     *
     * Binding (compatible = arm,cryptocell-312):
     *   $ZEPHYR_BASE\dts\bindings\crypto\arm,cryptocell-312.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_PATH "/soc/crypto@50844000/crypto@50845000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FULL_NAME "crypto@50845000"
    
    /* Node parent (/soc/crypto@50844000) identifier: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_PARENT DT_N_S_soc_S_crypto_50844000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_ORD 78
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REQUIRES_ORDS \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	77, /* /soc/crypto@50844000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_EXISTS 1
    #define DT_N_INST_0_arm_cryptocell_312 DT_N_S_soc_S_crypto_50844000_S_crypto_50845000
    #define DT_N_NODELABEL_cryptocell312   DT_N_S_soc_S_crypto_50844000_S_crypto_50845000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_NUM 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_VAL_ADDRESS 1350848512 /* 0x50845000 */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_RANGES_NUM 0
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_NUM 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_irq 68
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_MATCHES_arm_cryptocell_312 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_MODEL_IDX_0 "cryptocell-312"
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg {1350848512 /* 0x50845000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_0 1350848512
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 0) \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 1)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 1)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts {68 /* 0x44 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_0 68
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 0) \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 1)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 1)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible {"arm,cryptocell-312"}
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0 "arm,cryptocell-312"
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0_STRING_UNQUOTED arm,cryptocell-312
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0_STRING_TOKEN arm_cryptocell_312
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CRYPTOCELL_312
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, compatible, 0)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, compatible, 0)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_LEN 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_wakeup_source 0
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/adc@e000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000
     *
     * Binding (compatible = nordic,nrf-saadc):
     *   $ZEPHYR_BASE\dts\bindings\adc\nordic,nrf-saadc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PATH "/soc/peripheral@50000000/adc@e000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME "adc@e000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_IDX 20
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD 79
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000
    #define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_50000000_S_adc_e000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0 "nrf-saadc"
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"}
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc"
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/clock@5000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000
     *
     * Binding (compatible = nordic,nrf-clock):
     *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PATH "/soc/peripheral@50000000/clock@5000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME "clock@5000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD 80
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000
    #define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_50000000_S_clock_5000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0 "nrf-clock"
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"}
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock"
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/comparator@1a000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000
     *
     * Binding (compatible = nordic,nrf-comp):
     *   $ZEPHYR_BASE\dts\bindings\adc\nordic,nrf-comp.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PATH "/soc/peripheral@50000000/comparator@1a000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME "comparator@1a000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_IDX 29
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_ORD 81
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_comp DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000
    #define DT_N_NODELABEL_comp         DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_ADDRESS 1342283776 /* 0x5001a000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq 26
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MATCHES_nordic_nrf_comp 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0 "nrf-comp"
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg {106496 /* 0x1a000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0 106496
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts {26 /* 0x1a */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0 26
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible {"nordic,nrf-comp"}
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0 "nordic,nrf-comp"
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-comp
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_comp
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_COMP
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/ctrlap@6000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000
     *
     * Binding (compatible = nordic,nrf-ctrlapperi):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ctrlapperi.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PATH "/soc/peripheral@50000000/ctrlap@6000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME "ctrlap@6000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_IDX 6
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_ORD 82
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_ctrlapperi DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000
    #define DT_N_NODELABEL_ctrlap             DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_ADDRESS 1342201856 /* 0x50006000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MATCHES_nordic_nrf_ctrlapperi 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0 "nrf-ctrlapperi"
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg {24576 /* 0x6000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0 24576
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible {"nordic,nrf-ctrlapperi"}
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0 "nordic,nrf-ctrlapperi"
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ctrlapperi
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ctrlapperi
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CTRLAPPERI
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/dcnf@0
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dcnf_0
     *
     * Binding (compatible = nordic,nrf-dcnf):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dcnf.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PATH "/soc/peripheral@50000000/dcnf@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME "dcnf@0"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_ORD 83
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_dcnf DT_N_S_soc_S_peripheral_50000000_S_dcnf_0
    #define DT_N_NODELABEL_dcnf         DT_N_S_soc_S_peripheral_50000000_S_dcnf_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MATCHES_nordic_nrf_dcnf 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0 "nrf-dcnf"
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible {"nordic,nrf-dcnf"}
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0 "nordic,nrf-dcnf"
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dcnf
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dcnf
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DCNF
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/dppic@17000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
     *
     * Binding (compatible = nordic,nrf-dppic):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dppic.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PATH "/soc/peripheral@50000000/dppic@17000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME "dppic@17000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_IDX 26
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD 84
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
    #define DT_N_NODELABEL_dppic         DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0 "nrf-dppic"
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"}
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic"
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@1b000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PATH "/soc/peripheral@50000000/egu@1b000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME "egu@1b000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_IDX 30
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD 85
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
    #define DT_N_NODELABEL_egu0        DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@1c000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PATH "/soc/peripheral@50000000/egu@1c000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME "egu@1c000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_IDX 31
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD 86
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
    #define DT_N_NODELABEL_egu1        DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@1d000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PATH "/soc/peripheral@50000000/egu@1d000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME "egu@1d000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_IDX 32
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD 87
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
    #define DT_N_NODELABEL_egu2        DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@1e000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PATH "/soc/peripheral@50000000/egu@1e000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME "egu@1e000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_IDX 33
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD 88
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1
    #define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
    #define DT_N_NODELABEL_egu3        DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@1f000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PATH "/soc/peripheral@50000000/egu@1f000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME "egu@1f000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_IDX 34
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD 89
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1
    #define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
    #define DT_N_NODELABEL_egu4        DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/egu@20000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000
     *
     * Binding (compatible = nordic,nrf-egu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PATH "/soc/peripheral@50000000/egu@20000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME "egu@20000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_IDX 35
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD 90
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1
    #define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000
    #define DT_N_NODELABEL_egu5        DT_N_S_soc_S_peripheral_50000000_S_egu_20000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0 "nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu"
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2c@8000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
     *
     * Binding (compatible = nordic,nrf-twim):
     *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PATH "/soc/peripheral@50000000/i2c@8000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME "i2c@8000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_IDX 7
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD 91
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
    #define DT_N_NODELABEL_i2c0         DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0 "nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency 100000
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible {"nordic,nrf-twim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0 "nordic,nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2c@b000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
     *
     * Binding (compatible = nordic,nrf-twim):
     *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PATH "/soc/peripheral@50000000/i2c@b000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME "i2c@b000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_IDX 14
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD 92
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
    #define DT_N_NODELABEL_i2c2         DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0 "nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency 100000
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible {"nordic,nrf-twim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0 "nordic,nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2c@c000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
     *
     * Binding (compatible = nordic,nrf-twim):
     *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PATH "/soc/peripheral@50000000/i2c@c000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME "i2c@c000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_IDX 17
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_ORD 93
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_EXISTS 1
    #define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
    #define DT_N_NODELABEL_i2c3         DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq 12
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MATCHES_nordic_nrf_twim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0 "nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0 49152
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0 12
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_clock_frequency 100000
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible {"nordic,nrf-twim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0 "nordic,nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2s@28000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
     *
     * Binding (compatible = nordic,nrf-i2s):
     *   $ZEPHYR_BASE\dts\bindings\i2s\nordic,nrf-i2s.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PATH "/soc/peripheral@50000000/i2s@28000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME "i2s@28000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_IDX 41
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD 94
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
    #define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0 "nrf-i2s"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source "PCLK32M_HFXO"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/ieee802154
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ieee802154
     *
     * Binding (compatible = nordic,nrf-ieee802154):
     *   $ZEPHYR_BASE\dts\bindings\ieee802154\nordic,nrf-ieee802154.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PATH "/soc/peripheral@50000000/ieee802154"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME "ieee802154"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_IDX 55
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_ORD 95
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_ieee802154 DT_N_S_soc_S_peripheral_50000000_S_ieee802154
    #define DT_N_NODELABEL_ieee802154         DT_N_S_soc_S_peripheral_50000000_S_ieee802154
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REG_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MATCHES_nordic_nrf_ieee802154 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0 "nrf-ieee802154"
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible {"nordic,nrf-ieee802154"}
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0 "nordic,nrf-ieee802154"
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ieee802154
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ieee802154
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IEEE802154
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/kmu@39000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
     *
     * Binding (compatible = nordic,nrf-kmu):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-kmu.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PATH "/soc/peripheral@50000000/kmu@39000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME "kmu@39000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_IDX 51
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD 96
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
    #define DT_N_NODELABEL_kmu         DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0 "nrf-kmu"
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"}
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu"
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-kmu
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_kmu
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_KMU
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/mutex@30000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mutex_30000
     *
     * Binding (compatible = nordic,nrf-mutex):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-mutex.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PATH "/soc/peripheral@50000000/mutex@30000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME "mutex@30000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_IDX 45
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_ORD 97
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_mutex DT_N_S_soc_S_peripheral_50000000_S_mutex_30000
    #define DT_N_NODELABEL_mutex         DT_N_S_soc_S_peripheral_50000000_S_mutex_30000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_ADDRESS 1342373888 /* 0x50030000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MATCHES_nordic_nrf_mutex 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0 "nrf-mutex"
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg {196608 /* 0x30000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0 196608
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible {"nordic,nrf-mutex"}
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0 "nordic,nrf-mutex"
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-mutex
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_mutex
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_MUTEX
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/nfct@2d000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000
     *
     * Binding (compatible = nordic,nrf-nfct):
     *   $ZEPHYR_BASE\dts\bindings\net\wireless\nordic,nrf-nfct.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PATH "/soc/peripheral@50000000/nfct@2d000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME "nfct@2d000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_IDX 44
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_ORD 98
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_nfct DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000
    #define DT_N_NODELABEL_nfct         DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_ADDRESS 1342361600 /* 0x5002d000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq 45
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MATCHES_nordic_nrf_nfct 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0 "nrf-nfct"
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg {184320 /* 0x2d000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0 184320
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts {45 /* 0x2d */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0 45
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible {"nordic,nrf-nfct"}
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0 "nordic,nrf-nfct"
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-nfct
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_nfct
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_NFCT
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/oscillator@4000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000
     *
     * Binding (compatible = nordic,nrf-oscillators):
     *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-oscillators.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PATH "/soc/peripheral@50000000/oscillator@4000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FULL_NAME "oscillator@4000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_ORD 99
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_oscillators DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000
    #define DT_N_NODELABEL_oscillators         DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MATCHES_nordic_nrf_oscillators 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MODEL_IDX_0 "nrf-oscillators"
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_0 16384
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible {"nordic,nrf-oscillators"}
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0 "nordic,nrf-oscillators"
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-oscillators
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_oscillators
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_OSCILLATORS
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/pdm@26000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
     *
     * Binding (compatible = nordic,nrf-pdm):
     *   $ZEPHYR_BASE\dts\bindings\audio\nordic,nrf-pdm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PATH "/soc/peripheral@50000000/pdm@26000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME "pdm@26000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_IDX 40
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD 100
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
    #define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0 "nrf-pdm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source "PCLK32M_HFXO"
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size 4
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/pwm@22000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
     *
     * Binding (compatible = nordic,nrf-pwm):
     *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PATH "/soc/peripheral@50000000/pwm@22000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME "pwm@22000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_IDX 37
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD 101
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
    #define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0 "nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/pwm@23000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
     *
     * Binding (compatible = nordic,nrf-pwm):
     *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PATH "/soc/peripheral@50000000/pwm@23000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME "pwm@23000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_IDX 38
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD 102
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
    #define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0 "nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/pwm@24000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
     *
     * Binding (compatible = nordic,nrf-pwm):
     *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PATH "/soc/peripheral@50000000/pwm@24000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME "pwm@24000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_IDX 39
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD 103
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1
    #define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
    #define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0 "nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm"
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/qdec@33000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_33000
     *
     * Binding (compatible = nordic,nrf-qdec):
     *   $ZEPHYR_BASE\dts\bindings\sensor\nordic,nrf-qdec.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PATH "/soc/peripheral@50000000/qdec@33000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME "qdec@33000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_IDX 46
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_ORD 104
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_33000
    #define DT_N_NODELABEL_qdec0        DT_N_S_soc_S_peripheral_50000000_S_qdec_33000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_ADDRESS 1342386176 /* 0x50033000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq 51
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MATCHES_nordic_nrf_qdec 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0 "nrf-qdec"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg {208896 /* 0x33000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0 208896
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts {51 /* 0x33 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0 51
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible {"nordic,nrf-qdec"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0 "nordic,nrf-qdec"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/qdec@34000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_34000
     *
     * Binding (compatible = nordic,nrf-qdec):
     *   $ZEPHYR_BASE\dts\bindings\sensor\nordic,nrf-qdec.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PATH "/soc/peripheral@50000000/qdec@34000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME "qdec@34000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_IDX 47
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_ORD 105
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_34000
    #define DT_N_NODELABEL_qdec1        DT_N_S_soc_S_peripheral_50000000_S_qdec_34000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_ADDRESS 1342390272 /* 0x50034000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq 52
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MATCHES_nordic_nrf_qdec 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0 "nrf-qdec"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg {212992 /* 0x34000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0 212992
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts {52 /* 0x34 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0 52
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible {"nordic,nrf-qdec"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0 "nordic,nrf-qdec"
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/regulator@4000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
     *
     * Binding (compatible = nordic,nrf-regulators):
     *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-regulators.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PATH "/soc/peripheral@50000000/regulator@4000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME "regulator@4000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD 106
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
    #define DT_N_NODELABEL_regulators         DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0 "nrf-regulators"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf-regulators"}
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf-regulators"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-regulators
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_regulators
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_REGULATORS
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/regulator@37000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_37000
     *
     * Binding (compatible = nordic,nrf-usbreg):
     *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-usbreg.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PATH "/soc/peripheral@50000000/regulator@37000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME "regulator@37000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_IDX 49
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_ORD 107
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_usbreg DT_N_S_soc_S_peripheral_50000000_S_regulator_37000
    #define DT_N_NODELABEL_usbreg         DT_N_S_soc_S_peripheral_50000000_S_regulator_37000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_ADDRESS 1342402560 /* 0x50037000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq 55
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MATCHES_nordic_nrf_usbreg 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0 "nrf-usbreg"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg {225280 /* 0x37000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0 225280
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts {55 /* 0x37 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0 55
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible {"nordic,nrf-usbreg"}
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0 "nordic,nrf-usbreg"
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbreg
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbreg
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBREG
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/reset-controller@5000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000
     *
     * Binding (compatible = nordic,nrf-reset):
     *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-reset.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PATH "/soc/peripheral@50000000/reset-controller@5000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME "reset-controller@5000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_IDX 5
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_ORD 108
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_reset DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000
    #define DT_N_NODELABEL_reset         DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MATCHES_nordic_nrf_reset 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0 "nrf-reset"
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0 20480
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible {"nordic,nrf-reset"}
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0 "nordic,nrf-reset"
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-reset
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_reset
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RESET
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/rtc@14000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
     *
     * Binding (compatible = nordic,nrf-rtc):
     *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PATH "/soc/peripheral@50000000/rtc@14000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME "rtc@14000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_IDX 24
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD 109
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
    #define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0 "nrf-rtc"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num 4
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/rtc@15000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
     *
     * Binding (compatible = nordic,nrf-rtc):
     *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PATH "/soc/peripheral@50000000/rtc@15000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME "rtc@15000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_IDX 25
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD 110
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
    #define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0 "nrf-rtc"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num 4
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"}
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc"
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@8000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000
     *
     * Binding (compatible = nordic,nrf-spim):
     *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PATH "/soc/peripheral@50000000/spi@8000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME "spi@8000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_IDX 8
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD 111
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_8000
    #define DT_N_NODELABEL_spi0         DT_N_S_soc_S_peripheral_50000000_S_spi_8000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0 "nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible {"nordic,nrf-spim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0 "nordic,nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@9000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000
     *
     * Binding (compatible = nordic,nrf-spim):
     *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PATH "/soc/peripheral@50000000/spi@9000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME "spi@9000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_IDX 11
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD 112
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1
    #define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_9000
    #define DT_N_NODELABEL_spi1         DT_N_S_soc_S_peripheral_50000000_S_spi_9000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0 "nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible {"nordic,nrf-spim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0 "nordic,nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@a000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000
     *
     * Binding (compatible = nordic,nrf-spim):
     *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PATH "/soc/peripheral@50000000/spi@a000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME "spi@a000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_IDX 13
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD 113
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	30, /* /soc/peripheral@50000000/gpio@842800 */ \
    	50, /* /pin-controller/spi4_default */ \
    	52, /* /pin-controller/spi4_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000
    #define DT_N_NODELABEL_spi4         DT_N_S_soc_S_peripheral_50000000_S_spi_a000
    #define DT_N_NODELABEL_arduino_spi  DT_N_S_soc_S_peripheral_50000000_S_spi_a000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0 "nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi4_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi4_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi4_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency 32000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin 11
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi4_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@c000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_c000
     *
     * Binding (compatible = nordic,nrf-spim):
     *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PATH "/soc/peripheral@50000000/spi@c000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME "spi@c000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_IDX 18
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_ORD 114
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_EXISTS 1
    #define DT_N_INST_4_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_c000
    #define DT_N_NODELABEL_spi3         DT_N_S_soc_S_peripheral_50000000_S_spi_c000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq 12
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MATCHES_nordic_nrf_spim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0 "nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0 49152
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0 12
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible {"nordic,nrf-spim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0 "nordic,nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/timer@f000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000
     *
     * Binding (compatible = nordic,nrf-timer):
     *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PATH "/soc/peripheral@50000000/timer@f000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME "timer@f000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_IDX 21
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD 115
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000
    #define DT_N_NODELABEL_timer0        DT_N_S_soc_S_peripheral_50000000_S_timer_f000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0 "nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num 6
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width 32
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/timer@10000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000
     *
     * Binding (compatible = nordic,nrf-timer):
     *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PATH "/soc/peripheral@50000000/timer@10000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME "timer@10000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_IDX 22
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD 116
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000
    #define DT_N_NODELABEL_timer1        DT_N_S_soc_S_peripheral_50000000_S_timer_10000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0 "nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num 6
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width 32
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/timer@11000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000
     *
     * Binding (compatible = nordic,nrf-timer):
     *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PATH "/soc/peripheral@50000000/timer@11000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME "timer@11000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_IDX 23
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD 117
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000
    #define DT_N_NODELABEL_timer2        DT_N_S_soc_S_peripheral_50000000_S_timer_11000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0 "nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num 6
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width 32
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"}
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer"
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/uart@8000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000
     *
     * Binding (compatible = nordic,nrf-uarte):
     *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PATH "/soc/peripheral@50000000/uart@8000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME "uart@8000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_IDX 9
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD 118
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	54, /* /pin-controller/uart0_default */ \
    	57, /* /pin-controller/uart0_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_N_NODELABEL_uart0         DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0 "nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed 115200
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_ENUM_IDX 12
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart0_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/uart@9000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000
     *
     * Binding (compatible = nordic,nrf-uarte):
     *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PATH "/soc/peripheral@50000000/uart@9000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME "uart@9000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_IDX 12
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD 119
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	59, /* /pin-controller/uart1_default */ \
    	62, /* /pin-controller/uart1_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_uarte  DT_N_S_soc_S_peripheral_50000000_S_uart_9000
    #define DT_N_NODELABEL_uart1          DT_N_S_soc_S_peripheral_50000000_S_uart_9000
    #define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_peripheral_50000000_S_uart_9000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0 "nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed 115200
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_ENUM_IDX 12
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart1_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/uart@b000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000
     *
     * Binding (compatible = nordic,nrf-uarte):
     *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PATH "/soc/peripheral@50000000/uart@b000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME "uart@b000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_IDX 16
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD 120
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1
    #define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000
    #define DT_N_NODELABEL_uart2         DT_N_S_soc_S_peripheral_50000000_S_uart_b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0 "nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/uart@c000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_c000
     *
     * Binding (compatible = nordic,nrf-uarte):
     *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PATH "/soc/peripheral@50000000/uart@c000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME "uart@c000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_IDX 19
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_ORD 121
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_EXISTS 1
    #define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_c000
    #define DT_N_NODELABEL_uart3         DT_N_S_soc_S_peripheral_50000000_S_uart_c000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq 12
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MATCHES_nordic_nrf_uarte 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0 "nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0 49152
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0 12
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible {"nordic,nrf-uarte"}
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0 "nordic,nrf-uarte"
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/usbd@36000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
     *
     * Binding (compatible = nordic,nrf-usbd):
     *   $ZEPHYR_BASE\dts\bindings\usb\nordic,nrf-usbd.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PATH "/soc/peripheral@50000000/usbd@36000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME "usbd@36000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_IDX 48
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_ORD 122
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_usbd DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
    #define DT_N_NODELABEL_usbd         DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
    #define DT_N_NODELABEL_zephyr_udc0  DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_ADDRESS 1342398464 /* 0x50036000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq 54
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MATCHES_nordic_nrf_usbd 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0 "nrf-usbd"
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg {221184 /* 0x36000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0 221184
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts {54 /* 0x36 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0 54
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints 7
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints 7
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible {"nordic,nrf-usbd"}
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0 "nordic,nrf-usbd"
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbd
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbd
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBD
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/vmc@81000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
     *
     * Binding (compatible = nordic,nrf-vmc):
     *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PATH "/soc/peripheral@50000000/vmc@81000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME "vmc@81000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_IDX 52
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_ORD 123
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
    #define DT_N_NODELABEL_vmc         DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_ADDRESS 1342705664 /* 0x50081000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MATCHES_nordic_nrf_vmc 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0 "nrf-vmc"
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg {528384 /* 0x81000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0 528384
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible {"nordic,nrf-vmc"}
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0 "nordic,nrf-vmc"
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vmc
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vmc
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VMC
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/watchdog@18000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
     *
     * Binding (compatible = nordic,nrf-wdt):
     *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-wdt.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PATH "/soc/peripheral@50000000/watchdog@18000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME "watchdog@18000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_IDX 27
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD 124
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1
    #define DT_N_ALIAS_watchdog0       DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
    #define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
    #define DT_N_NODELABEL_wdt         DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
    #define DT_N_NODELABEL_wdt0        DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0 "nrf-wdt"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-wdt"}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-wdt"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/watchdog@19000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
     *
     * Binding (compatible = nordic,nrf-wdt):
     *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-wdt.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PATH "/soc/peripheral@50000000/watchdog@19000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME "watchdog@19000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_IDX 28
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_ORD 125
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
    #define DT_N_NODELABEL_wdt1        DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_ADDRESS 1342279680 /* 0x50019000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq 25
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MATCHES_nordic_nrf_wdt 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0 "nrf-wdt"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg {102400 /* 0x19000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0 102400
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0 25
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible {"nordic,nrf-wdt"}
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0 "nordic,nrf-wdt"
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
     *
     * Binding (compatible = nordic,nrf53-flash-controller):
     *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf53-flash-controller.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PATH "/soc/peripheral@50000000/flash-controller@39000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME "flash-controller@39000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_IDX 50
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD 126
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_SUPPORTS_ORDS \
    	127, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf53_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
    #define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf53_flash_controller 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0 "nrf53-flash-controller"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf53-flash-controller"}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf53-flash-controller"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-flash-controller
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_flash_controller
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_FLASH_CONTROLLER
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
     *
     * Binding (compatible = soc-nv-flash):
     *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME "flash@0"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD 127
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \
    	126, /* /soc/peripheral@50000000/flash-controller@39000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1
    #define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
    #define DT_N_NODELABEL_flash0    DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
     *
     * Binding (compatible = fixed-partitions):
     *   $ZEPHYR_BASE\dts\bindings\mtd\fixed-partitions.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME "partitions"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 128
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \
    	127, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \
    	129, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 */ \
    	130, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \
    	131, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \
    	132, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000 */ \
    	133, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000 */ \
    	134, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1
    #define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM 0
    
    /* (No generic property macros) */
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 129
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
    #define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 130
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
    #define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UNQUOTED image-0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN image_0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN IMAGE_0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 262144 /* 0x40000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 262144
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME "partition@50000"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX 2
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD 131
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS 1
    #define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS 327680 /* 0x50000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID 2
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label "image-0-nonsecure"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UNQUOTED image-0-nonsecure
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN image_0_nonsecure
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN IMAGE_0_NONSECURE
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg {327680 /* 0x50000 */, 196608 /* 0x30000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0 327680
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1 196608
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME "partition@80000"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX 3
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD 132
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS 1
    #define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS 524288 /* 0x80000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID 3
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label "image-1"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UNQUOTED image-1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN image_1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN IMAGE_1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg {524288 /* 0x80000 */, 262144 /* 0x40000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0 524288
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1 262144
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME "partition@c0000"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX 4
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD 133
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS 1
    #define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS 786432 /* 0xc0000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID 4
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label "image-1-nonsecure"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UNQUOTED image-1-nonsecure
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN image_1_nonsecure
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN IMAGE_1_NONSECURE
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg {786432 /* 0xc0000 */, 196608 /* 0x30000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0 786432
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1 196608
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME "partition@f8000"
    
    /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_CHILD_IDX 5
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_ORD 134
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REQUIRES_ORDS \
    	128, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_EXISTS 1
    #define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_ADDRESS 1015808 /* 0xf8000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PINCTRL_NUM 0
    
    /* fixed-partitions identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PARTITION_ID 5
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label "storage"
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UNQUOTED storage
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_TOKEN storage
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UPPER_TOKEN STORAGE
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_read_only 0
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_read_only_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg {1015808 /* 0xf8000 */, 32768 /* 0x8000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0 1015808
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1 32768
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2c@9000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
     *
     * Binding (compatible = nordic,nrf-twim):
     *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PATH "/soc/peripheral@50000000/i2c@9000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME "i2c@9000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_IDX 10
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD 135
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	33, /* /pin-controller/i2c1_default */ \
    	35, /* /pin-controller/i2c1_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_SUPPORTS_ORDS \
    	136, /* /soc/peripheral@50000000/i2c@9000/ST25V@1 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
    #define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
    #define DT_N_NODELABEL_arduino_i2c  DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0 "nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size 256
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size 16
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency 400000
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_i2c1_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/i2c@9000/ST25V@1
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_PATH "/soc/peripheral@50000000/i2c@9000/ST25V@1"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FULL_NAME "ST25V@1"
    
    /* Node parent (/soc/peripheral@50000000/i2c@9000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_PARENT DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_ORD 136
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_REQUIRES_ORDS \
    	135, /* /soc/peripheral@50000000/i2c@9000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_EXISTS 1
    #define DT_N_INST_0_i2c_device DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1
    #define DT_N_NODELABEL_st25v   DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1
    
    /* Bus info (controller: '/soc/peripheral@50000000/i2c@9000', type: '['i2c']') */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_BUS_i2c 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_BUS DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_COMPAT_MATCHES_i2c_device 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible {"i2c-device"}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_IDX_0 "i2c-device"
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_IDX_0_STRING_UNQUOTED i2c-device
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_IDX_0_STRING_TOKEN i2c_device
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_IDX_0_STRING_UPPER_TOKEN I2C_DEVICE
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg {1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_IDX_0 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1_P_reg_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/power@5000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000
     *
     * Binding (compatible = nordic,nrf-power):
     *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PATH "/soc/peripheral@50000000/power@5000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME "power@5000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_IDX 4
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD 137
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_SUPPORTS_ORDS \
    	138, /* /soc/peripheral@50000000/power@5000/gpregret1@551c */ \
    	139, /* /soc/peripheral@50000000/power@5000/gpregret2@5520 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000
    #define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_50000000_S_power_5000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0 "nrf-power"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret1@551c
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c
     *
     * Binding (compatible = nordic,nrf-gpregret):
     *   $ZEPHYR_BASE\dts\bindings\retained_mem\nordic,nrf-gpreget.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_PATH "/soc/peripheral@50000000/power@5000/gpregret1@551c"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FULL_NAME "gpregret1@551c"
    
    /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_ORD 138
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_REQUIRES_ORDS \
    	137, /* /soc/peripheral@50000000/power@5000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c
    #define DT_N_NODELABEL_gpregret1        DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_REG_IDX_0_VAL_ADDRESS 21788 /* 0x551c */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_COMPAT_MATCHES_nordic_nrf_gpregret 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_COMPAT_MODEL_IDX_0 "nrf-gpregret"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg {21788 /* 0x551c */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_IDX_0 21788
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible {"nordic,nrf-gpregret"}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_IDX_0 "nordic,nrf-gpregret"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret2@5520
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520
     *
     * Binding (compatible = nordic,nrf-gpregret):
     *   $ZEPHYR_BASE\dts\bindings\retained_mem\nordic,nrf-gpreget.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_PATH "/soc/peripheral@50000000/power@5000/gpregret2@5520"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FULL_NAME "gpregret2@5520"
    
    /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_CHILD_IDX 1
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_ORD 139
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_REQUIRES_ORDS \
    	137, /* /soc/peripheral@50000000/power@5000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520
    #define DT_N_NODELABEL_gpregret2        DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_REG_IDX_0_VAL_ADDRESS 21792 /* 0x5520 */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_COMPAT_MATCHES_nordic_nrf_gpregret 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_COMPAT_MODEL_IDX_0 "nrf-gpregret"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg {21792 /* 0x5520 */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_IDX_0 21792
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible {"nordic,nrf-gpregret"}
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_IDX_0 "nordic,nrf-gpregret"
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520_P_zephyr_pm_device_runtime_auto_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/qspi@2b000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
     *
     * Binding (compatible = nordic,nrf-qspi):
     *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf-qspi.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PATH "/soc/peripheral@50000000/qspi@2b000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME "qspi@2b000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_IDX 43
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_ORD 140
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	41, /* /pin-controller/qspi_default */ \
    	43, /* /pin-controller/qspi_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_SUPPORTS_ORDS \
    	141, /* /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_EXISTS 1
    #define DT_N_INST_0_nordic_nrf_qspi DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
    #define DT_N_NODELABEL_qspi         DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS 1342353408 /* 0x5002b000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS 268435456 /* 0x10000000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE 268435456 /* 0x10000000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq 43
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MATCHES_nordic_nrf_qspi 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0 "nrf-qspi"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_STATUS_disabled 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_qspi_default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts {43 /* 0x2b */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0 43
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_qspi_default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_qspi_default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg {176128 /* 0x2b000 */, 4096 /* 0x1000 */, 268435456 /* 0x10000000 */, 268435456 /* 0x10000000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0 176128
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2 268435456
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3 268435456
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status "disabled"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UNQUOTED disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_TOKEN disabled
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_UPPER_TOKEN DISABLED
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 7)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 7, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible {"nordic,nrf-qspi"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0 "nordic,nrf-qspi"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qspi
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qspi
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QSPI
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names {"qspi", "qspi_mm"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0 "qspi"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UNQUOTED qspi
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_TOKEN qspi
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UPPER_TOKEN QSPI
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1 "qspi_mm"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UNQUOTED qspi_mm
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_TOKEN qspi_mm
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UPPER_TOKEN QSPI_MM
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_qspi_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0
     *
     * Binding (compatible = nordic,qspi-nor):
     *   $ZEPHYR_BASE\dts\bindings\mtd\nordic,qspi-nor.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PATH "/soc/peripheral@50000000/qspi@2b000/mx25r6435f@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FULL_NAME "mx25r6435f@0"
    
    /* Node parent (/soc/peripheral@50000000/qspi@2b000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_ORD 141
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REQUIRES_ORDS \
    	140, /* /soc/peripheral@50000000/qspi@2b000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_EXISTS 1
    #define DT_N_ALIAS_spi_flash0       DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0
    #define DT_N_INST_0_nordic_qspi_nor DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0
    #define DT_N_NODELABEL_mx25r64      DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0
    
    /* Bus info (controller: '/soc/peripheral@50000000/qspi@2b000', type: '['qspi']') */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_BUS_qspi 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_BUS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MATCHES_nordic_qspi_nor 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0 "qspi-nor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg {0 /* 0x0 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_IDX_0 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id {194 /* 0xc2 */, 40 /* 0x28 */, 23 /* 0x17 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_0 194
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_1 40
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_2 23
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_2_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_LEN 3
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_size 67108864
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements "S1B6"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UNQUOTED S1B6
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_TOKEN S1B6
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UPPER_TOKEN S1B6
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_IDX 2
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_TOKEN S1B6
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_UPPER_TOKEN S1B6
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc "read4io"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_UNQUOTED read4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_TOKEN read4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_UPPER_TOKEN READ4IO
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_ENUM_IDX 4
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_ENUM_TOKEN read4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_ENUM_UPPER_TOKEN READ4IO
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 6)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 6, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc "pp4io"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_UNQUOTED pp4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_TOKEN pp4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_UPPER_TOKEN PP4IO
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_ENUM_IDX 3
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_ENUM_TOKEN pp4io
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_ENUM_UPPER_TOKEN PP4IO
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 4)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 4)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 4, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 4, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_address_size_32 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_address_size_32_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_ppsize_512 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_ppsize_512_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_delay 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_delay_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpha 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpha_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpol 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpol_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible {"nordic,qspi-nor"}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0 "nordic,qspi-nor"
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,qspi-nor
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_TOKEN nordic_qspi_nor
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_QSPI_NOR
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_requires_ulbpr 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_requires_ulbpr_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_has_dpd 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_has_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_enter_dpd 10000
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_enter_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_exit_dpd 35000
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_exit_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 3 /* 0x3 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 4 /* 0x4 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 35 /* 0x23 */, 114 /* 0x72 */, 245 /* 0xf5 */, 0 /* 0x0 */, 130 /* 0x82 */, 237 /* 0xed */, 4 /* 0x4 */, 204 /* 0xcc */, 68 /* 0x44 */, 131 /* 0x83 */, 104 /* 0x68 */, 68 /* 0x44 */, 48 /* 0x30 */, 176 /* 0xb0 */, 48 /* 0x30 */, 176 /* 0xb0 */, 247 /* 0xf7 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 190 /* 0xbe */, 41 /* 0x29 */, 255 /* 0xff */, 240 /* 0xf0 */, 208 /* 0xd0 */, 255 /* 0xff */, 255 /* 0xff */}
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0 229
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1 32
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2 241
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7 3
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8 68
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9 235
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10 8
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11 107
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12 8
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13 59
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14 4
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15 187
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16 238
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28 12
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29 32
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30 15
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31 82
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32 16
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33 216
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36 35
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37 114
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38 245
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40 130
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41 237
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42 4
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43 204
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44 68
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45 131
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46 104
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47 68
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48 48
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49 176
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50 48
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51 176
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52 247
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53 196
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54 213
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55 92
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56 0
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57 190
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58 41
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60 240
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61 208
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63 255
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_LEN 64
    #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@b000
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000
     *
     * Binding (compatible = nordic,nrf-spim):
     *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PATH "/soc/peripheral@50000000/spi@b000"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME "spi@b000"
    
    /* Node parent (/soc/peripheral@50000000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_IDX 15
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, __VA_ARGS__)
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD 142
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REQUIRES_ORDS \
    	8, /* /soc/peripheral@50000000 */ \
    	21, /* /soc/interrupt-controller@e000e100 */ \
    	30, /* /soc/peripheral@50000000/gpio@842800 */ \
    	46, /* /pin-controller/spi2_default */ \
    	48, /* /pin-controller/spi2_sleep */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_SUPPORTS_ORDS \
    	143, /* /soc/peripheral@50000000/spi@b000/mx25l16test@0 */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1
    #define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000
    #define DT_N_NODELABEL_spi2         DT_N_S_soc_S_peripheral_50000000_S_spi_b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0 "nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NUM 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi2_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi2_sleep
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi2_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi2_default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_0, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin 15
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, cs_gpios, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_cs_gpios_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "okay"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UNQUOTED okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_IDX 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_TOKEN okay
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN OKAY
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi2_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi2_sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_1, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names {"default", "sleep"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0 "default"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_TOKEN default
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1 "sleep"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, pinctrl_names, 1, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_LEN 2
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_pinctrl_names_EXISTS 1
    
    /*
     * Devicetree node: /soc/peripheral@50000000/spi@b000/mx25l16test@0
     *
     * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0
     *
     * Binding (compatible = jedec,spi-nor):
     *   $ZEPHYR_BASE\dts\bindings\mtd\jedec,spi-nor.yaml
     *
     * (Descriptions have moved to the Devicetree Bindings Index
     * in the documentation.)
     */
    
    /* Node's full path: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_PATH "/soc/peripheral@50000000/spi@b000/mx25l16test@0"
    
    /* Node's name with unit-address: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FULL_NAME "mx25l16test@0"
    
    /* Node parent (/soc/peripheral@50000000/spi@b000) identifier: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_spi_b000
    
    /* Node's index in its parent's list of children: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_CHILD_IDX 0
    
    /* Helper macros for child nodes of this node. */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_STATUS_OKAY(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 
    
    /* Node's dependency ordinal: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_ORD 143
    
    /* Ordinals for what this node depends on directly: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_REQUIRES_ORDS \
    	142, /* /soc/peripheral@50000000/spi@b000 */
    
    /* Ordinals for what depends directly on this node: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_SUPPORTS_ORDS /* nothing */
    
    /* Existence and alternate IDs: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_EXISTS 1
    #define DT_N_INST_0_jedec_spi_nor DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0
    #define DT_N_NODELABEL_mx25l16    DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0
    
    /* Bus info (controller: '/soc/peripheral@50000000/spi@b000', type: '['spi']') */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_BUS_spi 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_BUS DT_N_S_soc_S_peripheral_50000000_S_spi_b000
    
    /* Macros for properties that are special in the specification: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_REG_NUM 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_REG_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_RANGES_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_FOREACH_RANGE(fn) 
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_IRQ_NUM 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_COMPAT_MATCHES_jedec_spi_nor 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_COMPAT_VENDOR_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_COMPAT_VENDOR_IDX_0 "JEDEC Solid State Technology Association"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_COMPAT_MODEL_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_COMPAT_MODEL_IDX_0 "spi-nor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_STATUS_okay 1
    
    /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_PINCTRL_NUM 0
    
    /* Generic property macros: */
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg {0 /* 0x0 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_IDX_0 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, reg, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, reg, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_reg_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_spi_max_frequency 8000000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_spi_max_frequency_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_duplex 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_duplex_ENUM_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_duplex_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_frame_format 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_frame_format_ENUM_IDX 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_frame_format_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible {"jedec,spi-nor"}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_IDX_0 "jedec,spi-nor"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_IDX_0_STRING_UNQUOTED jedec,spi-nor
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_IDX_0_STRING_TOKEN jedec_spi_nor
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_IDX_0_STRING_UPPER_TOKEN JEDEC_SPI_NOR
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, compatible, 0)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, compatible, 0, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_LEN 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_compatible_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label "MX25L16TEST"
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_STRING_UNQUOTED MX25L16TEST
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_STRING_TOKEN MX25L16TEST
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_STRING_UPPER_TOKEN MX25L16TEST
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 10)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 10)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 10, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, label, 10, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_label_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_wakeup_source 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_wakeup_source_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_zephyr_pm_device_runtime_auto 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_requires_ulbpr 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_requires_ulbpr_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_has_dpd 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_has_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_t_enter_dpd 10000
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_t_enter_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_t_exit_dpd 8800
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_t_exit_dpd_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id {194 /* 0xc2 */, 32 /* 0x20 */, 21 /* 0x15 */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_0 194
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_1 32
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_2 21
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_IDX_2_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 2)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 2)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 2, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, jedec_id, 2, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_LEN 3
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_jedec_id_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_size 16777216
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_size_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 129 /* 0x81 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 63 /* 0x3f */, 0 /* 0x0 */, 0 /* 0x0 */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 8 /* 0x8 */, 59 /* 0x3b */, 0 /* 0x0 */, 255 /* 0xff */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */}
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_0 229
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_0_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_1 32
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_1_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_2 129
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_2_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_3 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_3_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_4 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_4_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_5 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_5_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_6 63
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_6_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_7 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_7_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_8 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_8_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_9 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_9_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_10 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_10_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_11 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_11_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_12 8
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_12_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_13 59
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_13_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_14 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_14_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_15 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_15_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_16 238
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_16_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_17 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_17_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_18 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_18_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_19 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_19_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_20 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_20_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_21 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_21_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_22 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_22_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_23 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_23_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_24 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_24_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_25 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_25_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_26 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_26_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_27 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_27_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_28 12
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_28_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_29 32
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_29_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_30 16
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_30_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_31 216
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_31_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_32 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_32_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_33 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_33_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_34 0
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_34_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_35 255
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_IDX_35_EXISTS 1
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 0) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 1) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 2) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 3) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 4) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 5) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 6) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 7) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 8) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 9) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 10) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 11) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 12) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 13) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 14) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 15) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 16) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 17) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 18) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 19) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 20) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 21) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 22) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 23) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 24) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 25) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 26) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 27) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 28) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 29) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 30) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 31) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 32) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 33) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 34) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 35)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 35)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 0, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 1, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 2, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 3, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 4, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 5, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 6, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 7, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 8, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 9, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 10, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 11, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 12, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 13, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 14, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 15, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 16, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 17, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 18, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 19, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 20, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 21, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 22, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 23, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 24, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 25, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 26, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 27, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 28, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 29, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 30, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 31, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 32, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 33, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 34, __VA_ARGS__) \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 35, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
    	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, sfdp_bfp, 35, __VA_ARGS__)
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_LEN 36
    #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0_P_sfdp_bfp_EXISTS 1
    
    /*
     * Chosen nodes
     */
    #define DT_CHOSEN_zephyr_entropy                          DT_N_S_soc_S_crypto_50844000
    #define DT_CHOSEN_zephyr_entropy_EXISTS                   1
    #define DT_CHOSEN_zephyr_flash_controller                 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
    #define DT_CHOSEN_zephyr_flash_controller_EXISTS          1
    #define DT_CHOSEN_zephyr_console                          DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_CHOSEN_zephyr_console_EXISTS                   1
    #define DT_CHOSEN_zephyr_shell_uart                       DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_CHOSEN_zephyr_shell_uart_EXISTS                1
    #define DT_CHOSEN_zephyr_uart_mcumgr                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS               1
    #define DT_CHOSEN_zephyr_bt_mon_uart                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS               1
    #define DT_CHOSEN_zephyr_bt_c2h_uart                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
    #define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS               1
    #define DT_CHOSEN_zephyr_bt_hci_rpmsg_ipc                 DT_N_S_ipc_S_ipc0
    #define DT_CHOSEN_zephyr_bt_hci_rpmsg_ipc_EXISTS          1
    #define DT_CHOSEN_nordic_802154_spinel_ipc                DT_N_S_ipc_S_ipc0
    #define DT_CHOSEN_nordic_802154_spinel_ipc_EXISTS         1
    #define DT_CHOSEN_zephyr_ieee802154                       DT_N_S_soc_S_peripheral_50000000_S_ieee802154
    #define DT_CHOSEN_zephyr_ieee802154_EXISTS                1
    #define DT_CHOSEN_zephyr_ipc_shm                          DT_N_S_reserved_memory_S_memory_20070000
    #define DT_CHOSEN_zephyr_ipc_shm_EXISTS                   1
    #define DT_CHOSEN_zephyr_sram                             DT_N_S_reserved_memory_S_image_20000000
    #define DT_CHOSEN_zephyr_sram_EXISTS                      1
    #define DT_CHOSEN_zephyr_flash                            DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
    #define DT_CHOSEN_zephyr_flash_EXISTS                     1
    #define DT_CHOSEN_zephyr_code_partition                   DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
    #define DT_CHOSEN_zephyr_code_partition_EXISTS            1
    #define DT_CHOSEN_zephyr_sram_secure_partition            DT_N_S_reserved_memory_S_image_s_20000000
    #define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS     1
    #define DT_CHOSEN_zephyr_sram_non_secure_partition        DT_N_S_reserved_memory_S_image_ns_20040000
    #define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1
    #define DT_CHOSEN_nordic_pm_ext_flash                     DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0
    #define DT_CHOSEN_nordic_pm_ext_flash_EXISTS              1
    
    /* Macros for iterating over all nodes and enabled nodes */
    #define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000) fn(DT_N_S_soc_S_gpiote_4002f000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_default_S_group1) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_nrf_gpio_forwarder_S_uart) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_default_S_group1) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_nrf_gpio_forwarder_S_uart) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000)
    #define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
    #define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
    #define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
    #define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
    #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
    #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1
    #define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
    #define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
    #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
    #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1
    #define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000
    #define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1
    
    /*
     * Macros for compatibles with status "okay" nodes
     */
    #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_dk_nrf5340_cpuapp 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp_qkaa 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf53 1
    #define DT_COMPAT_HAS_OKAY_simple_bus 1
    #define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
    #define DT_COMPAT_HAS_OKAY_mmio_sram 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_dcnf 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_oscillators 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpregret 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_reset 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_ctrlapperi 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_twim 1
    #define DT_COMPAT_HAS_OKAY_i2c_device 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
    #define DT_COMPAT_HAS_OKAY_jedec_spi_nor 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1
    #define DT_COMPAT_HAS_OKAY_nordic_mbox_nrf_ipc 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1
    #define DT_COMPAT_HAS_OKAY_nordic_qspi_nor 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_nfct 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_mutex 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_usbd 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_usbreg 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf53_flash_controller 1
    #define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
    #define DT_COMPAT_HAS_OKAY_fixed_partitions 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_ieee802154 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_cc312 1
    #define DT_COMPAT_HAS_OKAY_arm_cryptocell_312 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1
    #define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1
    #define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
    #define DT_COMPAT_HAS_OKAY_arm_armv8m_itm 1
    #define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
    #define DT_COMPAT_HAS_OKAY_zephyr_ipc_openamp_static_vrings 1
    #define DT_COMPAT_HAS_OKAY_gpio_leds 1
    #define DT_COMPAT_HAS_OKAY_pwm_leds 1
    #define DT_COMPAT_HAS_OKAY_gpio_keys 1
    #define DT_COMPAT_HAS_OKAY_arduino_header_r3 1
    #define DT_COMPAT_HAS_OKAY_arduino_uno_adc 1
    #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio_forwarder 1
    
    /*
     * Macros for status "okay" instances of each compatible
     */
    #define DT_N_INST_nordic_nrf5340_dk_nrf5340_cpuapp_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf5340_cpuapp_qkaa_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf5340_cpuapp_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf53_NUM_OKAY 1
    #define DT_N_INST_simple_bus_NUM_OKAY 1
    #define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
    #define DT_N_INST_mmio_sram_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_dcnf_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_oscillators_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_regulators_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_gpregret_NUM_OKAY 2
    #define DT_N_INST_nordic_nrf_reset_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_ctrlapperi_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_twim_NUM_OKAY 1
    #define DT_N_INST_i2c_device_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_spim_NUM_OKAY 2
    #define DT_N_INST_jedec_spi_nor_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
    #define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 1
    #define DT_N_INST_nordic_mbox_nrf_ipc_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1
    #define DT_N_INST_nordic_qspi_nor_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_nfct_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_mutex_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_usbd_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_usbreg_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf53_flash_controller_NUM_OKAY 1
    #define DT_N_INST_soc_nv_flash_NUM_OKAY 1
    #define DT_N_INST_fixed_partitions_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2
    #define DT_N_INST_nordic_nrf_ieee802154_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_cc312_NUM_OKAY 1
    #define DT_N_INST_arm_cryptocell_312_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1
    #define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1
    #define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
    #define DT_N_INST_arm_armv8m_itm_NUM_OKAY 1
    #define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
    #define DT_N_INST_zephyr_ipc_openamp_static_vrings_NUM_OKAY 1
    #define DT_N_INST_gpio_leds_NUM_OKAY 1
    #define DT_N_INST_pwm_leds_NUM_OKAY 1
    #define DT_N_INST_gpio_keys_NUM_OKAY 1
    #define DT_N_INST_arduino_header_r3_NUM_OKAY 1
    #define DT_N_INST_arduino_uno_adc_NUM_OKAY 1
    #define DT_N_INST_nordic_nrf_gpio_forwarder_NUM_OKAY 1
    #define DT_FOREACH_OKAY_nordic_nrf5340_dk_nrf5340_cpuapp(fn) fn(DT_N)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_dk_nrf5340_cpuapp(fn, ...) fn(DT_N, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf5340_dk_nrf5340_cpuapp(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_dk_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp_qkaa(fn) fn(DT_N_S_soc)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp_qkaa(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp(fn) fn(DT_N_S_soc)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf53(fn) fn(DT_N_S_soc)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf53(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf53(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
    #define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
    #define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ff0000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_ff8000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000)
    #define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_dcnf(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_dcnf(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_dcnf(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dcnf(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_oscillators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_oscillators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_oscillators(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_oscillators(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_regulators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_gpregret(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpregret(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_551c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_5520, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_gpregret(fn) fn(0) fn(1)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpregret(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_reset(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_reset(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_reset(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_reset(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_ctrlapperi(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_ctrlapperi(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_twim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_twim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_i2c_device(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1)
    #define DT_FOREACH_OKAY_VARGS_i2c_device(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_st25v_1, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_i2c_device(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_i2c_device(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0) fn(1)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
    #define DT_FOREACH_OKAY_jedec_spi_nor(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0)
    #define DT_FOREACH_OKAY_VARGS_jedec_spi_nor(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000_S_mx25l16test_0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_jedec_spi_nor(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_jedec_spi_nor(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_dppic(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_pwm(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pwm(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pwm(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_mbox_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000)
    #define DT_FOREACH_OKAY_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_mbox_nrf_ipc(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_qspi_nor(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0)
    #define DT_FOREACH_OKAY_VARGS_nordic_qspi_nor(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_qspi_nor(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_qspi_nor(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_nfct(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_nfct(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_nfct(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_nfct(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_mutex(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_mutex(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_mutex(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_mutex(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_usbd(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_usbd(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_usbd(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_usbd(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_usbreg(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_usbreg(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_usbreg(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_usbreg(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf53_flash_controller(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf53_flash_controller(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
    #define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
    #define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_kmu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_vmc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_ieee802154(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ieee802154(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_ieee802154(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ieee802154(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_spu(fn) fn(DT_N_S_soc_S_spu_50003000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spu(fn, ...) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spu(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_5000d000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_cc312(fn) fn(DT_N_S_soc_S_crypto_50844000)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_cc312(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_cc312(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_cc312(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arm_cryptocell_312(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)
    #define DT_FOREACH_OKAY_VARGS_arm_cryptocell_312(fn, ...) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arm_cryptocell_312(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_312(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci)
    #define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0)
    #define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arm_armv8m_itm(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
    #define DT_FOREACH_OKAY_VARGS_arm_armv8m_itm(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arm_armv8m_itm(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_itm(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arm_armv8m_mpu(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
    #define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_zephyr_ipc_openamp_static_vrings(fn) fn(DT_N_S_ipc_S_ipc0)
    #define DT_FOREACH_OKAY_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_zephyr_ipc_openamp_static_vrings(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
    #define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds)
    #define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_buttons)
    #define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_buttons, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arduino_header_r3(fn) fn(DT_N_S_connector)
    #define DT_FOREACH_OKAY_VARGS_arduino_header_r3(fn, ...) fn(DT_N_S_connector, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arduino_header_r3(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arduino_header_r3(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_arduino_uno_adc(fn) fn(DT_N_S_analog_connector)
    #define DT_FOREACH_OKAY_VARGS_arduino_uno_adc(fn, ...) fn(DT_N_S_analog_connector, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_arduino_uno_adc(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_arduino_uno_adc(fn, ...) fn(0, __VA_ARGS__)
    #define DT_FOREACH_OKAY_nordic_nrf_gpio_forwarder(fn) fn(DT_N_S_nrf_gpio_forwarder)
    #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio_forwarder(fn, ...) fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__)
    #define DT_FOREACH_OKAY_INST_nordic_nrf_gpio_forwarder(fn) fn(0)
    #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio_forwarder(fn, ...) fn(0, __VA_ARGS__)
    
    /*
     * Bus information for status "okay" nodes of each compatible
     */
    #define DT_COMPAT_i2c_device_BUS_i2c 1
    #define DT_COMPAT_jedec_spi_nor_BUS_spi 1
    #define DT_COMPAT_nordic_qspi_nor_BUS_qspi 1
    

    Best regards,

    Georg

  • You are correct, just a hickup from my side regarding the devicetree.h

    Can you verify CONFIG_FLASH_MAP=y is set in prj.conf?

    Regards

    Runar

  • Hi Runar,

    CONFIG_FLASH_MAP=y is set in my prj.conf.

    I think I found a solution but don't understand how it works.

    When adding CONFIG_MULTITHREADING=y in the prj.conf file then

    the error "undefined reference to `__device_dts_ord_144'" disappears.

    When removing CONFIG_GPIO=y from the prj.conf file then the error "undefined reference to `__device_dts_ord_30'" disappears.

    Any ideas why this works ?

    Best Regards

    Georg

Reply
  • Hi Runar,

    CONFIG_FLASH_MAP=y is set in my prj.conf.

    I think I found a solution but don't understand how it works.

    When adding CONFIG_MULTITHREADING=y in the prj.conf file then

    the error "undefined reference to `__device_dts_ord_144'" disappears.

    When removing CONFIG_GPIO=y from the prj.conf file then the error "undefined reference to `__device_dts_ord_30'" disappears.

    Any ideas why this works ?

    Best Regards

    Georg

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