Can't set "Extra High Drive" for GPIO

[Mattias]

Hi,

As described in the subject I'm not able to set "Extra High Drive" for a GPIO. This setting is described in 7.13.5.11 in product specification version 1.3. I'm able to set "H0H1" by masking with 0x00000300 in the gpio_pin_configure_dt function. I see that the result is correct when I inspect with the debugger. If I instead mask with 0x00000B00, it seems like bit 10 and 11 are ignored. Is "Extra High Drive" supposed to work?

[Håkon Alseth]

Hi,

 

E0E1, as shown here:

https://infocenter.nordicsemi.com/topic/ps_nrf5340/gpio.html?cp=4_0_0_6_12_4_10#register.PIN_CNF

 

Is not handled by zephyr's gpio_nrfx.c driver:

https://github.com/nrfconnect/sdk-zephyr/blob/v3.4.99-ncs1-1/drivers/gpio/gpio_nrfx.c#L40

Thank you for making us aware of this and helping us improve our delivery! I will ensure that our low-level team is aware of this issue.

It is however handled by the nrf_gpio.h (struct nrf_gpio_pin_drive_t)

 

As a workaround for now, it would include writing to the NRF_Px->PIN_CNF[pin] register directly (or via nrf_gpio.h), unfortunately.

 

Kind regards,

Håkon

[Bjarki Andreasen]

The E0E1 drive configuration is not generic like H0H1, it is reserved for specific peripherals like the high-speed TWI, where it enables high power open-drain IO drivers for pins P1.02 and P1.03, and high speed TRACE IO drivers specifically for pins P0.08 - P0.12, see https://infocenter.nordicsemi.com/pdf/nRF5340_PS_v1.3.1.pdf section 9.1

Additionally, the Product specification states: For remaining pins "The E0E1 drive configuration is not supported. Using the E0E1 drive configuration will cause incorrect operation."

For this reason, the E0E1 drive configuration will not be exposed in the GPIO bindings, they are instead exposed in the pinctrl bindings, to be enabled for TWI, TRACE etc.