Async SPI example causes Zephyr exception in ncs v2.5.1

Hi,

I need to add SPI function to my project, according to this thread

 RE: SPI example for nRF52833 with nRF Connect SDK 2.3.0 

I download this async SPI example from github.

https://github.com/too1/ncs-spi-master-slave-example

When I run it in ncs v2.5.1, nRF52DK. I get the following RTT log

00> [00:00:00.425,720] <err> os: ***** Reserved Exception ( -16) *****
00> [00:00:00.425,720] <err> os: r0/a1:  0x200020c0  r1/a2:  0x00002151  r2/a3:  0x0000759b
00> [00:00:00.425,750] <err> os: r3/a4:  0x00002125 r12/ip:  0x00002125 r14/lr:  0x00002125
00> [00:00:00.425,750] <err> os:  xpsr:  0x00000000
00> [00:00:00.425,781] <err> os: Faulting instruction address (r15/pc): 0x00002125
00> [00:00:00.425,811] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
00> [00:00:00.425,842] <err> os: Current thread: 0x20000800 (main)
00> [00:00:01.240,417] <err> os: Halting system

and paused on spi_transceive_async()

Does spi_transceive_async() support in the ncs v2.5.1?

I attached my project file also, just add some configs for RTT log.

ncs-spi-master-slave-example-master.zip

Parents
  • HI,

    I just test with ncs v2.3.0, and it seems work.

    *** Booting Zephyr OS build v3.2.99-ncs2 ***
    SPI master/slave example started
    SPI SLAVE TX: 0x00, 0x00
    SPI TX: 0x00, 0x00
    SPI RX: 0x00, 0x00
    

    It seems the device tree for CS pin is different between ncs v2.5.1 and ncs v2.3.0?

  • Hello,

    That sample is supposed to work with NCS 2.3.0

    If you want to use the same project, then you must look at the SPI API and update the code accordingly.

    For example, I can see that the CS member of spi_config is of type "spi_cs_control" in NCS2.3.0, but is of type "spi_cs_control *" in the NCS.2.5.1. You need to update the code as per changes incorporated in the API, or Drivers, or the SDK.

    You can see and adapt changes through the release notes and migration guides (migration guides are not always available for every version): NCS releases_and_maturity

    Regards,

    Naeem

  • Hi  ,

    I don't see this SPI issue in the release notes and migration guides.

    So according to your reply, I modify spi_cfg to test,

    static const struct spi_config spi_cfg = {
    	.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB |
    				 SPI_MODE_CPOL | SPI_MODE_CPHA,
    	.frequency = 4000000,
    	.slave = 0,
    	//.cs = &spim_cs,
    
    	.cs.gpio.port = 0,
    	.cs.gpio.pin = 28,
    	.cs.gpio.dt_flags = GPIO_ACTIVE_LOW,
    	.cs.delay = 0,
    };

    It seems generate the clock and MOSI signals, but the CS pin would not active low during SPI.

Reply
  • Hi  ,

    I don't see this SPI issue in the release notes and migration guides.

    So according to your reply, I modify spi_cfg to test,

    static const struct spi_config spi_cfg = {
    	.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB |
    				 SPI_MODE_CPOL | SPI_MODE_CPHA,
    	.frequency = 4000000,
    	.slave = 0,
    	//.cs = &spim_cs,
    
    	.cs.gpio.port = 0,
    	.cs.gpio.pin = 28,
    	.cs.gpio.dt_flags = GPIO_ACTIVE_LOW,
    	.cs.delay = 0,
    };

    It seems generate the clock and MOSI signals, but the CS pin would not active low during SPI.

Children
Related