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Maximum sink current on nRF5340 for LED (Low Side Switches), which sink voltage level to use for resistor calculation?

puz_md

Hello,

We are using a nRF5340 at 3.3V to drive a RGB LED (common anode) on our system. Our PCB has very little space, so we cannot use external MOSFETs (we have to use the GPIO pins of the nRF5340 as low side switches for the LED). We have additionally three TWI communication interfaces (two over standard pins one over the the TWI dedicated pins) with 4.7k external pull-up on each signal line, which would result in a little more than 4 mA if all lines were pulled down by the TWI interface in worst case.

Recommended operating current for the LED is 10 mA for red and 5 mA for green and blue.

The product specification says:

If I would drive all LED channels with maximum brightness, I would sink 20...25 mA (including the TWI channels) into the nRF5340. Could this already impede stable operation of the nRF5340? Would it damage the SoC? I'm not sure what happens if we exceed the "recommended maximum current". Is it less critical if the current is sunk into the nRF5340 instead of drawn from it?

If it is a problem that we exceed the specified value, may the 15 mA be interpreted as an average current or are they even valid for peak current? (e.g. if I drive the LED in white with PWM where all three channels are synchronous, I sink 10 mA (plus TWI) in average, but 20 mA (plus TWI) peak at 50% duty cycle.

One more question, the product specification says the output voltage is between VSS and VSS+0.4V. If my green LED has a forward voltage of 2.7V, I have 0.6V left to "burn" outside of the LED. What voltage should I use to calculate the resistor for the LED? Using VSS would result in burning 0.6V at 5 mA, but using VSS+0.4V would result in burning only 0.2V at 5 mA, which would be a third of the previous resistor value...

Sorry for asking this question again, there were already some questing regarding GPIO current, but I couldn't find the details I'm looking for in them.

Best regards,

Michael

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  • 0

    Hi, Michael.

    Is it an option to use an LED with a lower operating current?

    If I would drive all LED channels with maximum brightness, I would sink 20...25 mA (including the TWI channels) into the nRF5340.

    Including all three TWI channels or only the two using the standard pins?

    Best regards,
    Mathias

  • 0 in reply to mathiaso

    Worst case for the LED would be 20 mA (10 mA for red, 5 mA each for green and blue) when used according to specification.

    TWI with 4.7k pull-up on both SDA and SCL means 1.4 mA worst case current (both lines pulled to low) for each TWI interface.

    So, worst case with all three channels would be around 24.2 mA (plus minimal extra current for driving one or two MOSFETs and the ADC), without the TWI dedicated pins it would be around 22.8 mA.

    We will try to keep the LED below 15 mA, but it is a bit tricky to calculate/estimate the actual current flow with a supply voltage as low as 3.3V for the RGB LED, especially under extreme temperature conditions that may affect LED forward current etc.

    That's why it would help to know which risks we face when exceeding the "recommended maximum current", so that we can include this in our failure mode considerations. (E.g. if the MCU crashes, we might still recover with a watchdog or user reset, but if the silicon is damaged, it would be bad for the customers.)

    Best regards,

    Michael

  • 0 in reply to puz_md

    You might consider only turning one LED on at a time; not quite as daft as it sounds, use non-overlapping PWM outputs for the 3 RGB pins such that they are multiplexed at a suitable no-flicker rate. Perceived brightness at (say) a 1/3 duty cycle is probably acceptable and this optionally allows brightness variation between RGB by modifying the mark:space ratio for each which in turn allows measuring VDD and tuning the M:S ratio to automatically compensate brightness depending on applied voltage. Somewhere there is a "dimming" algorithm in the examples, maybe have a look at that.

  • +1 in reply to puz_md

    Hi again, Michael.

    puz_md said:
    That's why it would help to know which risks we face when exceeding the "recommended maximum current", so that we can include this in our failure mode considerations. (E.g. if the MCU crashes, we might still recover with a watchdog or user reset, but if the silicon is damaged, it would be bad for the customers.)

    Unfortunately, I can't give you a definite answer to what happens if you sink more than 15 mA in total from the GPIOs but the limit is there for a reason. There is a possibility that you may damage something. Thus, I wouldn't recommend planning for a GPIOI current greater than 15 mA.

    One more question, the product specification says the output voltage is between VSS and VSS+0.4V. If my green LED has a forward voltage of 2.7V, I have 0.6V left to "burn" outside of the LED. What voltage should I use to calculate the resistor for the LED? Using VSS would result in burning 0.6V at 5 mA, but using VSS+0.4V would result in burning only 0.2V at 5 mA, which would be a third of the previous resistor value...

    In high drive, the inner resistance of the pad is approx. 17 Ω. If delivering 5 mA to a 2.7 V LED, you'll need a series resistance of 0.6 V / 5 mA - 17 Ω = 103 Ω. If the low voltage increases to VSS + 0.4 V and the voltage over the LED still is maintained at 2.7 V, you'll have a current of 0.2 V / 120 Ω = 1.7 mA.

    I guess the forward voltage over the LED will drop a bit when the low voltage increases (the datasheet will show you this), let's say 0.2 V, which leads to a current of 0.4 V / 120 Ω = 3.3 mA. I don't know within which regions the datasheet says the LED will be able to operate but this is something that should be possible to figure out.

    If you aren't able to find LEDs that both fit your needs and have sufficiently low forward current, maybe Hugh's suggestion might be something to look into.

  • 0 in reply to mathiaso

    Hi mathiaso,

    we'll be conservative with out resistors to keep the overall current below 15 mA then.

    Does this limit include the TWI specific pins (P1.02 and P1.03 on nRF5340), by the way? I was just wondering because you asked about them earlier. I guess normal operation will be included in the 15 mA limit, but if I use the special open drain configuration, it will not be included in the 15 mA limit:

    The E0E1 drive configuration activates a 20 mA open-drain driver specifically
    designed for high-speed TWI.
    mathiaso said:
    when the low voltage increases

    Do I understand correctly that the low voltage of a GPIO pin may float between VSS and VSS+0.4V randomly, independent of the current and the internal resistance? If a single GPIO pin would sink 15 mA, with 17 Ω of resistance, the voltage drop would be 0.255V, so the "+0.4V" is probably not caused by the GPIO's resistance (only). But is in the "+0.4V" the voltage drop caused by the resistance under worst conditions / highest allowable current included already? Or will I have to add it on top? (Just being a bit confused because you brought up the pad's inner resistance.)

    Best regards,

    Michael

  • +1 in reply to puz_md
    puz_md said:
    Does this limit include the TWI specific pins (P1.02 and P1.03 on nRF5340), by the way? I was just wondering because you asked about them earlier. I guess normal operation will be included in the 15 mA limit, but if I use the special open drain configuration, it will not be included in the 15 mA limit:

    If you have a look at the note to that 15 mA value, you'll see that the dedicated TWI pins are excluded, as long as the open drain driver is enabled.

    This is in accordance with what you were thinking and also what is described here.

    puz_md said:
    Do I understand correctly that the low voltage of a GPIO pin may float between VSS and VSS+0.4V randomly, independent of the current and the internal resistance? If a single GPIO pin would sink 15 mA, with 17 Ω of resistance, the voltage drop would be 0.255V, so the "+0.4V" is probably not caused by the GPIO's resistance (only). But is in the "+0.4V" the voltage drop caused by the resistance under worst conditions / highest allowable current included already? Or will I have to add it on top? (Just being a bit confused because you brought up the pad's inner resistance.)

    I'm afraid my previous explanation over-simplified things a bit and thus, turned out to be a bit confusing. The internal resistance isn't a constant resistance of 17 Ω but it varies with the change of current. 17 Ω is a typical value at lower current values. When the current is higher, the resistance will be lower.

    The difference in the low voltage is caused by the internal resistance. Hence, it will not be randomly fluctuating. The min./max. levels are there to also include the worst-case scenarios.

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  • +1 in reply to puz_md
    puz_md said:
    Does this limit include the TWI specific pins (P1.02 and P1.03 on nRF5340), by the way? I was just wondering because you asked about them earlier. I guess normal operation will be included in the 15 mA limit, but if I use the special open drain configuration, it will not be included in the 15 mA limit:

    If you have a look at the note to that 15 mA value, you'll see that the dedicated TWI pins are excluded, as long as the open drain driver is enabled.

    This is in accordance with what you were thinking and also what is described here.

    puz_md said:
    Do I understand correctly that the low voltage of a GPIO pin may float between VSS and VSS+0.4V randomly, independent of the current and the internal resistance? If a single GPIO pin would sink 15 mA, with 17 Ω of resistance, the voltage drop would be 0.255V, so the "+0.4V" is probably not caused by the GPIO's resistance (only). But is in the "+0.4V" the voltage drop caused by the resistance under worst conditions / highest allowable current included already? Or will I have to add it on top? (Just being a bit confused because you brought up the pad's inner resistance.)

    I'm afraid my previous explanation over-simplified things a bit and thus, turned out to be a bit confusing. The internal resistance isn't a constant resistance of 17 Ω but it varies with the change of current. 17 Ω is a typical value at lower current values. When the current is higher, the resistance will be lower.

    The difference in the low voltage is caused by the internal resistance. Hence, it will not be randomly fluctuating. The min./max. levels are there to also include the worst-case scenarios.

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