I am trying to communicate with NRF52832 on MRFC522 vscode. My Write and Read functions are not working

[damar]

Below I have my read and write functions. Are my SPI configuration settings correct? I want to read the RFID card ID value.

MAİN.C

#include <zephyr/drivers/gpio.h>

#include <zephyr/drivers/SPi.h>
#include "MRFC522.h"



/* The devicetree node identifier for the "led0" alias. */
#define LED0_NODE DT_ALIAS(led0)
uint8_t ID[5];
/*
 * A build error on this line means your board is unsupported.
 * See the sample documentation for information on how to fix this.
 */
static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios);

int main(void)
{
	int ret;
SPI_Init();
TM_MFRC522_Init();
	if (!gpio_is_ready_dt(&led)) {
		return 0;
	}

	ret = gpio_pin_configure_dt(&led, GPIO_OUTPUT_ACTIVE);
	if (ret < 0) {
		return 0;
	}

	while (1) {

    if ((TM_MFRC522_Check(ID) == MI_OK))
	{
		gpio_pin_toggle_dt(&led);
printk(" [%02x%02x%02x%02x%02x]\n\r\n", ID[0], ID[1], ID[2], ID[3], ID[4]);
	}

	
	
	}
	return 0;
}

[damar]

/* Pins Definition for lis3dsh */
#define SPI_SS_PIN   28  // pin to be connected to cs(chip select pin)
#define SPI_SCK_PIN  31  // pin to be connected to clock pin (scl)
#define SPI_MISO_PIN 29  // pin to be connected to MISO 
#define SPI_MOSI_PIN 30  // pin to be connected to MOSI


#define    SPIFlash_CS_LOW    nrf_gpio_pin_clear(SPI_SS_PIN)   // a simple function call to clear the cs pin
#define    SPIFlash_CS_HIGH   nrf_gpio_pin_set(SPI_SS_PIN)     //a simple function call to set the cs pin 



/* MFRC522 status */
typedef enum {
    MI_OK = 0,
    MI_NOTAGERR,
    MI_ERR
} TM_MFRC522_STS_T;

/* MFRC522 commands */
#define PCD_IDLE						0x00   // No action; Cancel the current command
#define PCD_AUTHENT						0x0E   // Authentication Key
#define PCD_RECEIVE						0x08   // Receive Data
#define PCD_TRANSMIT					0x04   // Transmit data
#define PCD_TRANSCEIVE					0x0C   // Transmit and receive data,
#define PCD_RESETPHASE					0x0F   // Reset
#define PCD_CALCCRC						0x03   // CRC Calculate

/* Mifare One card command word */
#define PICC_REQA						0x26   // find the antenna area does not enter hibernation
#define PICC_WAKEUP						0x52   // find all the cards antenna area
#define PICC_ANTICOLL					0x93   // anti-collision
#define PICC_SElECTTAG					0x93   // election card
#define PICC_AUTHENT1A					0x60   // authentication key A
#define PICC_AUTHENT1B					0x61   // authentication key B
#define PICC_READ						0x30   // Read Block
#define PICC_WRITE						0xA0   // write block
#define PICC_DECREMENT					0xC0   // debit
#define PICC_INCREMENT					0xC1   // recharge
#define PICC_RESTORE					0xC2   // transfer block data to the buffer
#define PICC_TRANSFER					0xB0   // save the data in the buffer
#define PICC_HALT						0x50   // Sleep

/* MFRC522 Registers */
/* Page 0: Command and Status */
#define MFRC522_REG_RESERVED00			0x00    
#define MFRC522_REG_COMMAND				0x01    
#define MFRC522_REG_COMM_IE_N			0x02    
#define MFRC522_REG_DIV1_EN				0x03    
#define MFRC522_REG_COMM_IRQ			0x04    
#define MFRC522_REG_DIV_IRQ				0x05
#define MFRC522_REG_ERROR				0x06    
#define MFRC522_REG_STATUS1				0x07    
#define MFRC522_REG_STATUS2				0x08    
#define MFRC522_REG_FIFO_DATA			0x09
#define MFRC522_REG_FIFO_LEVEL			0x0A
#define MFRC522_REG_WATER_LEVEL			0x0B
#define MFRC522_REG_CONTROL				0x0C
#define MFRC522_REG_BIT_FRAMING			0x0D
#define MFRC522_REG_COLL				0x0E
#define MFRC522_REG_RESERVED01			0x0F

/* Page 1: Command */
#define MFRC522_REG_RESERVED10			0x10
#define MFRC522_REG_MODE				0x11
#define MFRC522_REG_TX_MODE				0x12
#define MFRC522_REG_RX_MODE				0x13
#define MFRC522_REG_TX_CONTROL			0x14
#define MFRC522_REG_TX_AUTO				0x15
#define MFRC522_REG_TX_SELL				0x16
#define MFRC522_REG_RX_SELL				0x17
#define MFRC522_REG_RX_THRESHOLD		0x18
#define MFRC522_REG_DEMOD				0x19
#define MFRC522_REG_RESERVED11			0x1A
#define MFRC522_REG_RESERVED12			0x1B
#define MFRC522_REG_MIFARE				0x1C
#define MFRC522_REG_RESERVED13			0x1D
#define MFRC522_REG_RESERVED14			0x1E
#define MFRC522_REG_SERIALSPEED			0x1F

/* Page 2: Configuration */
#define MFRC522_REG_RESERVED20			0x20  
#define MFRC522_REG_CRC_RESULT_M		0x21
#define MFRC522_REG_CRC_RESULT_L		0x22
#define MFRC522_REG_RESERVED21			0x23
#define MFRC522_REG_MOD_WIDTH			0x24
#define MFRC522_REG_RESERVED22			0x25
#define MFRC522_REG_RF_CFG				0x26
#define MFRC522_REG_GS_N				0x27
#define MFRC522_REG_CWGS_PREG			0x28
#define MFRC522_REG__MODGS_PREG			0x29
#define MFRC522_REG_T_MODE				0x2A
#define MFRC522_REG_T_PRESCALER			0x2B
#define MFRC522_REG_T_RELOAD_H			0x2C
#define MFRC522_REG_T_RELOAD_L			0x2D
#define MFRC522_REG_T_COUNTER_VALUE_H	0x2E
#define MFRC522_REG_T_COUNTER_VALUE_L	0x2F

/* Page 3:TestRegister */
#define MFRC522_REG_RESERVED30			0x30
#define MFRC522_REG_TEST_SEL1			0x31
#define MFRC522_REG_TEST_SEL2			0x32
#define MFRC522_REG_TEST_PIN_EN			0x33
#define MFRC522_REG_TEST_PIN_VALUE		0x34
#define MFRC522_REG_TEST_BUS			0x35
#define MFRC522_REG_AUTO_TEST			0x36
#define MFRC522_REG_VERSION				0x37
#define MFRC522_REG_ANALOG_TEST			0x38
#define MFRC522_REG_TEST_ADC1			0x39  
#define MFRC522_REG_TEST_ADC2			0x3A   
#define MFRC522_REG_TEST_ADC0			0x3B   
#define MFRC522_REG_RESERVED31			0x3C   
#define MFRC522_REG_RESERVED32			0x3D
#define MFRC522_REG_RESERVED33			0x3E   
#define MFRC522_REG_RESERVED34			0x3F

#define MFRC522_DUMMY					0x00
#define MFRC522_MAX_LEN					16

/*---------------------------------------------------------------------------------------------------------*/
/* Function declaration                                                                                    */
/*---------------------------------------------------------------------------------------------------------*/
//void MFRC522_Halt();
void SPI_Init(void); 
void TM_MFRC522_Init(void);
uint8_t TM_MFRC522_RdReg(uint8_t ucAddress);
void TM_MFRC522_WrReg(uint8_t ucAddress, uint8_t ucValue);
void TM_MFRC522_SetBitMask(uint8_t reg, uint8_t mask);
void TM_MFRC522_ClearBitMask(uint8_t reg, uint8_t mask);
void TM_MFRC522_AntennaOn(void);
void TM_MFRC522_AntennaOff(void);
void TM_MFRC522_Reset(void);
uint8_t MFRC522_ToCard(uint8_t command, uint8_t *sendData, uint8_t sendLen, uint8_t *backData,unsigned *backLen);
uint8_t MFRC522_isCard(uint8_t *TagType ) ;
TM_MFRC522_STS_T TM_MFRC522_ToCard(uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen);
TM_MFRC522_STS_T TM_MFRC522_Anticoll(uint8_t* serNum);
void TM_MFRC522_CalculateCRC(uint8_t*  pIndata, uint8_t len, uint8_t* pOutData);
void TM_MFRC522_Halt(void);
uint8_t TM_MFRC522_Check(uint8_t *id);
uint8_t MFRC522_Request(uint8_t reqMode, uint8_t *TagType);
#endif

[damar]

#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>


#define PICC_TIMEOUT_5MS    0x09
#define PICC_TIMEOUT_10MS   0x13
#define PICC_TIMEOUT_15MS   0x1E




    struct spi_buf_set tx_bufs;
    struct spi_buf_set rx_bufs;
	struct spi_buf txb;
	struct spi_buf rxb;



#define GPIO DT_NODELABEL(gpio0)
#define GPIO_CS 28
const struct device *gpio1_dev = DEVICE_DT_GET(GPIO);

const struct device *spi_dev = DEVICE_DT_GET(DT_NODELABEL(spi1)) ;

struct spi_config spi_cfg ;
struct spi_cs_control chip;


void SPI_Init(void)
{
  
 	if (!device_is_ready(spi_dev)) {
        /* Device is not ready to use */
		printk("\r\nStop device not ready\r\n");
	}
    
    chip.gpio.dt_flags = GPIO_ACTIVE_LOW;
    chip.gpio.pin = 28;
    chip.delay = 2;
	
    spi_cfg.frequency = 4000000;
    spi_cfg.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB |
				 SPI_MODE_CPOL | SPI_MODE_CPHA;
    spi_cfg.slave = 0;


 
}



void TM_MFRC522_WrReg(uint8_t ucAddress, uint8_t ucValue)
    {

      
    struct spi_buf_set tx_bufs;
	struct spi_buf txb[2];
    
    uint8_t command;
    command = ucAddress;

    txb[0].buf = &command;
	txb[0].len = 1;
    txb[1].buf = &ucValue;
	txb[1].len = 1;

	tx_bufs.buffers = (const struct spi_buf *)&txb;
	tx_bufs.count = 2;

	spi_transceive(spi_dev,&spi_cfg,&tx_bufs,&rx_bufs);

	}

    

uint8_t TM_MFRC522_RdReg(uint8_t ucAddress)
    {	
  

     uint16_t command = 0x80 | ucAddress;

    txb.buf = &command;
	txb.len = 1;
    tx_bufs.buffers = (const struct spi_buf *)&txb;
	tx_bufs.count = 1;

    rxb.buf = NULL;
	rxb.len = 1;
    rx_bufs.buffers = (const struct spi_buf *)&rxb;
	rx_bufs.count = 1;


	spi_transceive(spi_dev,&spi_cfg,&tx_bufs,&rx_bufs);

return *(uint8_t *)rx_bufs.buffers->buf;
  
}

void TM_MFRC522_Init(void)
    {

    TM_MFRC522_Reset();

    TM_MFRC522_WrReg(MFRC522_REG_T_MODE, 0x8D);
    TM_MFRC522_WrReg(MFRC522_REG_T_PRESCALER, 0x3E);

    TM_MFRC522_WrReg(MFRC522_REG_T_RELOAD_L, 0x09);
    TM_MFRC522_WrReg(MFRC522_REG_T_RELOAD_H, 0);

    TM_MFRC522_WrReg(MFRC522_REG_TX_AUTO, 0x40);
    TM_MFRC522_WrReg(MFRC522_REG_MODE, 0x3D);

    TM_MFRC522_WrReg(MFRC522_REG_RF_CFG, 0x70);

    TM_MFRC522_SetBitMask(MFRC522_REG_DIV1_EN, 0x80);

    TM_MFRC522_AntennaOn();


    }


/* A function to initialize SPI Instance */



void TM_MFRC522_SetBitMask(uint8_t reg, uint8_t mask)
    {
    TM_MFRC522_WrReg(reg, TM_MFRC522_RdReg(reg) | mask);
    }

void TM_MFRC522_ClearBitMask(uint8_t reg, uint8_t mask)
    {
    TM_MFRC522_WrReg(reg, TM_MFRC522_RdReg(reg) & (~mask));
    }

void TM_MFRC522_AntennaOn(void)
    {
    uint8_t temp;

    temp = TM_MFRC522_RdReg(MFRC522_REG_TX_CONTROL);
    if (!(temp & 0x03))
	TM_MFRC522_SetBitMask(MFRC522_REG_TX_CONTROL, 0x03);
    }

void TM_MFRC522_AntennaOff(void)
    {
    TM_MFRC522_ClearBitMask(MFRC522_REG_TX_CONTROL, 0x03);
    }

void TM_MFRC522_Reset(void)
    {
    uint8_t temp;

    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, PCD_RESETPHASE);

    do
	{
	temp = TM_MFRC522_RdReg(MFRC522_REG_COMMAND);
	temp &= 0x10;
	}
    while (temp);
    }

uint8_t MFRC522_ToCard(uint8_t command, uint8_t *sendData, uint8_t sendLen, uint8_t *backData,unsigned *backLen)
    {
    uint8_t _status = MI_ERR;
    uint8_t irqEn = 0x00;
    uint8_t waitIRq = 0x00;
    uint8_t lastBits;
    uint8_t n;
    unsigned i;

    switch (command)
	{
    case PCD_AUTHENT:
	{
	irqEn = 0x12;
	waitIRq = 0x10;
	break;
	}
    case PCD_TRANSCEIVE:
	{
	irqEn = 0x77;
	waitIRq = 0x30;
	break;
	}
    default:
	break;
	}

    TM_MFRC522_WrReg(MFRC522_REG_COMM_IE_N, irqEn | 0x80);
    TM_MFRC522_ClearBitMask(MFRC522_REG_COMM_IRQ, 0x80);
    TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);
    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, PCD_IDLE);

    for (i = 0; i < sendLen; i++)
	{
	TM_MFRC522_WrReg(MFRC522_REG_FIFO_DATA, sendData[i]);
	}

    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, command);

    if (command == PCD_TRANSCEIVE)
	{
	TM_MFRC522_SetBitMask(MFRC522_REG_BIT_FRAMING, 0x80);
	}

    i = 0xFFFF;
    do
	{

	n = TM_MFRC522_RdReg(MFRC522_REG_COMM_IRQ);
	i--;
	}
    while (i && !(n & 0x01) && !(n & waitIRq));

    TM_MFRC522_ClearBitMask(MFRC522_REG_BIT_FRAMING, 0x80);

    if (i != 0)
	{
	if (!(TM_MFRC522_RdReg(MFRC522_REG_ERROR) & 0x1B))
	    {
	    _status = MI_OK;
	    if (n & irqEn & 0x01)
		{
		_status = MI_NOTAGERR;
		}

	    if (command == PCD_TRANSCEIVE)
		{
		n = TM_MFRC522_RdReg(MFRC522_REG_FIFO_LEVEL);
		lastBits = TM_MFRC522_RdReg(MFRC522_REG_CONTROL) & 0x07;
		if (lastBits)
		    {
		    *backLen = (n - 1) * 8 + lastBits;
		    }
		else
		    {
		    *backLen = n * 8;
		    }

		if (n == 0)
		    {
		    n = 1;
		    }

		if (n > 16)
		    {
		    n = 16;
		    }

		for (i = 0; i < n; i++)
		    {
		    backData[i] = TM_MFRC522_RdReg(MFRC522_REG_FIFO_DATA);
		    }

		backData[i] = 0;
		}
	    }
	else
	    {
	    _status = MI_ERR;
	    }

	}

    return _status;
    }

uint8_t MFRC522_Request(uint8_t reqMode, uint8_t *TagType)
    {
    uint8_t _status;
    unsigned backBits;

    TM_MFRC522_WrReg(MFRC522_REG_BIT_FRAMING, 0x07);

    TagType[0] = reqMode;
    _status = MFRC522_ToCard(PCD_TRANSCEIVE, TagType, 1, TagType, &backBits);

    if ((_status != MI_OK) || (backBits != 0x10))
	{
	_status = MI_ERR;
	}

    return _status;
    }

uint8_t MFRC522_isCard(uint8_t *TagType)
    {
    if (MFRC522_Request(PICC_REQA, TagType) == MI_OK)

	return 1;
    else
	return 0;
    }
		
TM_MFRC522_STS_T TM_MFRC522_Anticoll(uint8_t* serNum)
{
    TM_MFRC522_STS_T status;
    uint8_t i;
    uint8_t serNumCheck = 0;
    uint16_t unLen;
	
		TM_MFRC522_ClearBitMask(MFRC522_REG_STATUS2,0x08);
    TM_MFRC522_WrReg(MFRC522_REG_BIT_FRAMING, 0x00);		//TxLastBists = BitFramingReg[2..0]
		TM_MFRC522_SetBitMask(MFRC522_REG_COLL,0x80);
	
    /* ANTICOLLISION command with NVB does not specify 40 valid bits (NVB not to 0x70) */
    /* Note: "NVB=0x20" defines that the PCD will transmit no part of UID CLn, and it forces all
             PICCs in the field to respond with their complete UID CLn. */
    serNum[0] = PICC_ANTICOLL;
    serNum[1] = 0x20;   // NVB
    status = TM_MFRC522_ToCard(PCD_TRANSCEIVE, serNum, 2, serNum, &unLen);

    if (status == MI_OK) {
        /* Check card serial number */
        for (i = 0; i < 4; i++) { 
					serNumCheck ^= serNum[i];					
        }
        
        /* BCC: UID CLn checkbyte and is calculated
           as exclusive-or over the 4 previous bytes */
        if (serNumCheck != serNum[i] ) {
            status = MI_ERR;    
        }
    }
		TM_MFRC522_SetBitMask(MFRC522_REG_COLL,0x80);
		
    return status;
} 

TM_MFRC522_STS_T TM_MFRC522_ToCard(uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen)
{
    TM_MFRC522_STS_T status = MI_ERR;
    uint8_t irqEn = 0x00;
		uint8_t waitFor = 0x00;
    uint8_t lastBits;
    uint8_t regValue;
    uint16_t i;
    
    switch (command)
    {
        case PCD_AUTHENT:
            irqEn = 0x13;
						waitFor = 0x10;
        //    irqEn = 0x12; (original setting)
            break;
        case PCD_TRANSCEIVE:
            /* TxIRq(b6), RxIRq(b5), IdleIRq(b4),
               HiAlerIRq(b3), LoAlertIRq(b2), ErrIRq(b1), TimerIRq(b0) */
            /* wait response from PICC or 5 ms timeout */
            irqEn = 0x21;
						waitFor = 0x30;
            break;
        default:
            break;
    }
    /* IRQ pin is inverted with respect to the Status1Reg register’s IRq bit */
    TM_MFRC522_WrReg(MFRC522_REG_COMM_IE_N, irqEn | 0x80);

    /* Clear marked bits in ComIrqReg register */
    TM_MFRC522_ClearBitMask(MFRC522_REG_COMM_IRQ, 0x80);
		
		TM_MFRC522_WrReg(MFRC522_REG_COMMAND,PCD_IDLE);

    /* Flush FIFO contents */
    TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);

    /* Cancel current comand execution */
    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, PCD_IDLE);

    /* Write data to FIFO */
    for (i = 0; i < sendLen; i++) {   
        TM_MFRC522_WrReg(MFRC522_REG_FIFO_DATA, sendData[i]);    
    }

    /* Execute PCD_TRANSCEIVE command */
    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, command);
    
    if (command == PCD_TRANSCEIVE) {    
        /* Start frame transmission */
        TM_MFRC522_SetBitMask(MFRC522_REG_BIT_FRAMING, 0x80);
    }   
			
		i = 1000;
    /* Wait response from PICC or internal timer 5 ms timeout happened */
    do
		{
			
    regValue = TM_MFRC522_RdReg(MFRC522_REG_COMM_IRQ);
		i--;
		}while ((i!=0) && !(regValue&0x01) && !(regValue&waitFor));
		
		
    /* Set StartSend=0 */
    TM_MFRC522_ClearBitMask(MFRC522_REG_BIT_FRAMING, 0x80);

    /* Check if internal timer timeout */
    if (!(regValue &0x01))
    {
        if(i!=0)
				{
        if (!(TM_MFRC522_RdReg(MFRC522_REG_ERROR) & 0x1B))
        {
            status = MI_OK;
            
            if (command == PCD_TRANSCEIVE)
            {
                /* Check the number of bytes stored in FIFO */
                regValue = TM_MFRC522_RdReg(MFRC522_REG_FIFO_LEVEL);
                
                /* Check valid bit number of last byte */
                lastBits = TM_MFRC522_RdReg(MFRC522_REG_CONTROL) & 0x07;
                if (lastBits)
                    *backLen = (regValue - 1) * 8 + lastBits;   
                else
                    *backLen = regValue * 8;

                if (regValue == 0)
                    regValue = 1;    
                if (regValue > MFRC522_MAX_LEN)
                    regValue = MFRC522_MAX_LEN;   

                /* Read received data in FIFO */
                for (i = 0; i < regValue; i++)
                    backData[i] = TM_MFRC522_RdReg(MFRC522_REG_FIFO_DATA);    
            }
        }
        else
				{status = MI_ERR;}
    }

}
		TM_MFRC522_SetBitMask(MFRC522_REG_CONTROL,0x80);
		TM_MFRC522_WrReg(MFRC522_REG_COMMAND,PCD_IDLE);
    return status;
		}


		
		
		
		

void TM_MFRC522_CalculateCRC(uint8_t *pIndata, uint8_t len, uint8_t *pOutData)
    {
    uint8_t i, n;

    TM_MFRC522_ClearBitMask(MFRC522_REG_DIV_IRQ, 0x04);

    TM_MFRC522_SetBitMask(MFRC522_REG_FIFO_LEVEL, 0x80);

    for (i = 0; i < len; i++)
	{
	TM_MFRC522_WrReg(MFRC522_REG_FIFO_DATA, *(pIndata + i));
	}
    TM_MFRC522_WrReg(MFRC522_REG_COMMAND, PCD_CALCCRC);

    i = 0xFF;
    do
	{
	n = TM_MFRC522_RdReg(MFRC522_REG_DIV_IRQ);
	i--;
	}
    while ((i != 0) && !(n & 0x04));

    pOutData[0] = TM_MFRC522_RdReg(MFRC522_REG_CRC_RESULT_L);
    pOutData[1] = TM_MFRC522_RdReg(MFRC522_REG_CRC_RESULT_M);
    }


void TM_MFRC522_Halt(void)
    {

    unsigned unLen;
    uint8_t buff[4];

    buff[0] = PICC_HALT;
    buff[1] = 0;
    TM_MFRC522_CalculateCRC(buff, 2, &buff[2]);

    if (MFRC522_ToCard(PCD_TRANSCEIVE, buff, 4, buff, &unLen) != MI_NOTAGERR)
	{
	printf("Halt command error. \n");
	}

    }

		
		uint8_t TM_MFRC522_Check(uint8_t *id)
    {
    uint8_t status;
    uint8_t cardtype[3];

    status = MFRC522_Request(PICC_REQA, cardtype);
    if (status == MI_OK)
	status = TM_MFRC522_Anticoll(id);
    else
	status = MI_ERR;
		
    return status;
		
    }