It is possible to synchronously start waveforms on 3 PWM peripherals on the nRF52832 using PPI and EGU with no phase delay between the 3 output waveforms - they start simultaneously and remain in phase.
#define SEQUENCE_SIZE 2
static uint16_t pwm_seq_0[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
static uint16_t pwm_seq_1[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
static uint16_t pwm_seq_2[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
// Map file output, nRF52832 with single RAM area
// pwm_seq_0 0x2000'08b8
// pwm_seq_1 0x2000'08bc
// pwm_seq_2 0x2000'08c0
Running the exact same code on the nRF52840 or nRF52833, with 3 or 4 PWM peripherals, produces a time/phase offset of 125nSec between each of the PWMS, ie gaps of 125, 250 and 375nSecs. My assumption was that this is caused by the PWM DMA Bus Master being stalled in priority order PWM0-PWM1-PWM2-PWM3, and so I forced the sequence data structure for each PWM to be in a different RAM Slave. This fixed the offset, no phase delay.
// Bus Slaves (RAM):
// Name AdrSpace StartAdr EndAdr AccType
// Memory = RAM0 Memory 0x20000000 0x20001FFF RW
// Memory = RAM1 Memory 0x20002000 0x20003FFF RW
// Memory = RAM2 Memory 0x20004000 0x20005FFF RW
// Memory = RAM3 Memory 0x20006000 0x20007FFF RW
// Memory = RAM4 Memory 0x20008000 0x20009FFF RW
// Memory = RAM5 Memory 0x2000A000 0x2000BFFF RW
// Memory = RAM6 Memory 0x2000C000 0x2000DFFF RW
// Memory = RAM7 Memory 0x2000E000 0x2000FFFF RW
// Memory = RAM8 Memory 0x20010000 0x2001FFFF RW
#define SEQUENCE_SIZE 2
#pragma location = 0x20006000
static uint16_t pwm_seq_0[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
#pragma location = 0x20008000
static uint16_t pwm_seq_1[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
#pragma location = 0x2000A000
static uint16_t pwm_seq_2[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
#pragma location = 0x2000C000
static uint16_t pwm_seq_3[SEQUENCE_SIZE] = {PWM_CH0_DUTY, PWM_CH1_DUTY};
// Map file output, nRF52833 with separate RAM areas
// pwm_seq_0 0x2000'6000
// pwm_seq_1 0x2000'8000
// pwm_seq_2 0x2000'a000
// pwm_seq_3 0x2000'c000
My questions: Why is the nRF52832 PWM different from the nRF52833 PWM? Are other peripherals affected in a similar manner? Will any other higher-priority Bus Master such as SPIM re-introduce a phase delay if active at the PPI trigger instant?
This investigation was initiated by trying to answer this case start-pwms-synchronous raised by karel
