When selecting the ACLK frequency of 11.2896 mhz and a sample rate of 48khz, zephyr panics with the error "division by zero".
The culprit is find_suitable_clock(). Posted a bug report on zephyr's git.
I've gotten around it by simply commenting out the function, because I bypass the clock division entirely, so there was no point in searching for clock combinations. I do realise I used the wrong ACLK value for a 48Khz sampling rate, but I thought it best to report it, since the PDM peripheral uses a similar function and there could be other combinations that yield erroneous results.
I suggest an assert or something that warns the user (like in my case), "hey, you selected a really dumb aclk value, here's an assert fail for you".
There's really no point in continuing this thread, I just wanted to make sure this gets back to you. Thanks for your time.
