SPI Master Example Code: Clk & MOSI Signal Error

[jiamin]

Hi,

I am trying to set up an SPI communication between nordic nrf52 (as a master) and another slave peripheral. I'm using nrf52 sdks 0.9.2. I tried spi master loopback example and spi master with slave example, and both seemed to be working, with the led indicator blinking correctly.

I modified spi master with slave example a little bit, simply commenting out the buff_check() and reducing the transmission & receiving buffer to 2 bytes, so that I could use it to communicate with a slave device. However, I'm not getting any signals back to MISO.

When I checked the spi signals on oscilloscope, they seemed to be distorted and not synchronised with the sclk.

For example:

1. m_tx_data[0] = 0xff; m_tx_data[1] = 0x00;

   MOSI, SCLK, CS signals (though clk a bit distorted) seemed to be okay in this case:

   

2. m_tx_data[0] = 0xaa; m_tx_data[1] = 0xaa; MOSI not synchronised with SCLK.

3. m_tx_data[0] = 0x80; m_tx_data[1] = 0x80; MOSI lagged behind 7 SCLK cycles.

The SCLK actually seemed less distorted if I tested it on oscilloscope alone:

Any suggestions on why this is happening?

Your help will be very much appreciated!

Best Regards. Jiamin:)

[RK]

What is in your SPI CONFIG register? It looks to me that you're shifting out the least significant bit first, instead of the most significant bit. If you are doing that, all those traces are perfect, it's not 7 bits of lag, it's the 7 lowest 0s first followed by the 1

I'd say you have the ORDER field in CONFIG set to '1' == LsbFirst

[jiamin]

I see... Yes you are right.
The signals look alright after changing the ORDER config setting to MsbFirst.

Thanks a lot for your help:)