Hello,
I am reaching out regarding some challenges I've encountered with SPI communication on the nRF7002DK when interfacing with the ETH Wiz Click | Mikroe module and a Voltage-Level Shifter. Specifically, I've been experiencing difficulties while attempting to use the SPI4 peripheral to achieve higher speeds. The code tested is essentially the sample code for the DHCP_v4 client.
Initially, I used the SPI3 peripheral and the communication proceeded as expected. Below is an excerpt from the overlay file used:
&spi3 {
status = "okay";
w5500@0 {
compatible = "wiznet,w5500";
reg = <0x0>;
spi-max-frequency = <DT_FREQ_K(7999)>;
int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
};
Furthermore, I observed an anomaly where specifying an exact frequency of 8 MHz for the "spi-max-frequency" property resulted in data bus errors. However, setting it slightly lower, at 7.99 MHz, appeared to alleviate this issue.
However, when I try to use the SPI4 to take advantage of higher SPI speeds, the communication doesn't seem to occur. The capture with a logic analyzer is shown below as well as the terminal output:
[00:00:00.275,543] <err> eth_w5500: Unable to read version register *** Booting nRF Connect SDK d96769faceca *** [00:00:00.483,154] <inf> net_dhcpv4_client_sample: Run dhcpv4 client [00:00:00.483,184] <inf> net_dhcpv4_client_sample: Start on w5500@0: index=1 [00:00:00.483,245] <inf> net_dhcpv4_client_sample: NET_EVENT_IPV4_DHCP_START [00:00:00.483,428] <inf> net_dhcpv4_client_sample: Start on nordic_wlan0: index= 2 [00:00:00.483,489] <inf> net_dhcpv4_client_sample: NET_EVENT_IPV4_DHCP_START
The overlay file to use with the SPI4 node is shown below:
&spi4 {
/delete-node/ mx25r6435f@0;
w5500@0 {
compatible = "wiznet,w5500";
reg = <0x0>;
spi-max-frequency = <1000000>;
int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
};
The communication failed to happen successfully. Despite various troubleshooting attempts, including removing the MX25R node from the overlay file, lower the clock frequency down to 1MHz or configure the pins to high drive, I've yet to resolve this issue.
I am reaching out to seek guidance on potential oversights or misconfigurations that might be contributing to this issue. Any insights or recommendations you could provide would be greatly appreciated.
Thank you for your attention to this matter. I look forward to your response.
