Hello,
I am using an nRF5340dk to create a PPI Timer as shown in the following code block:
static void set_ppi_clock() {
nrfx_gpiote_init(GPIOTE_INTERRUPT_PRIORITY);
LOG_DBG("GPIOTE initialized.");
nrfx_err_t err;
nrfx_gpiote_out_config_t out_config = NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(false);
// TODO :: update depricated function call of nrfx_gpio_out_init();
// NOTE: This function is deprecated. Use nrfx_gpiote_output_configure preceded by nrfx_gpiote_channel_alloc
// (provided that GPIOTE task is to be utilized) instead.
err = nrfx_gpiote_out_init(PIN, &out_config);
nrf_gpio_cfg(
PIN,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_H0H1,
NRF_GPIO_PIN_NOSENSE
);
if( err != NRFX_SUCCESS )
{
LOG_ERR("err_code not 0 for nrf_drv_gpiote_in_init");
}
nrfx_timer_config_t timer_cfg = NRFX_TIMER_DEFAULT_CONFIG;
timer_cfg.mode = NRF_TIMER_MODE_TIMER;
timer_cfg.bit_width = NRF_TIMER_BIT_WIDTH_32;
err = nrfx_timer_init(&m_timer, &timer_cfg, NULL);
ERROR_STATUS_CHECK(err)
nrfx_timer_extended_compare(&m_timer, NRF_TIMER_CC_CHANNEL0, CONFIG_MCLOCK_DIVIDER, NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK, false);
uint8_t channel;
err = nrfx_dppi_channel_alloc(&channel);
nrfx_gpiote_pin_t gpiote_mclk_sync_pin_out = PIN;
uint32_t gpiote_mclk_toggle_task_addr = nrfx_gpiote_out_task_addr_get(gpiote_mclk_sync_pin_out);
uint32_t timer_event_address = nrfx_timer_event_address_get(&m_timer, NRF_TIMER_EVENT_COMPARE0);
LOG_DBG("%x %x", gpiote_mclk_sync_pin_out, timer_event_address);
nrfx_gppi_channel_endpoints_setup(channel, timer_event_address, gpiote_mclk_toggle_task_addr);
nrfx_gppi_channels_enable(BIT(channel));
nrfx_gpiote_out_task_enable(PIN);
nrfx_timer_enable(&m_timer);
}This code behaves as expected when the clock divider is 1 or 2 (my PIN toggles at 16Mhz/2*divider, ~8.02Mhz and ~4.01Mhz, respectively), but when I change the clock divider to 3, I get a weird output frequency of 2.67Mhz, and I have no idea why this is. I read over section 7.1.36 TIMER - Timer/counter of the nRF5340 data sheet to try and understand better, but from my understanding, the PCLK16M should be used even at a divider of 3, so I don't understand why the output frequency is so far off from the expected ~2Mhz. I could maybe understand if the input clock to the prescaler changed from the 16M to the 1M but I don't see how that could be the case here. Please advise.
