Using spi3 on nRF9161

I am using PHYTEC link board eth (https://docs.zephyrproject.org/latest/boards/shields/link_board_eth/doc/index.html) as ethernet shield using SPI on nRF9161. 

I updated the VDD rail voltage to 3.3V using the board configurator and also verified using a multimeter. 

The shield uses the following pins for the SPI connection . 

D9   - INT
D10 - CS
D11 - MOSI
D12 - MISO
D13 - SCK

In nrf9161_nrf9161_common.dtsi, gd25wb256 is disabled. spi3 status is "okay".

arduino_spi: &spi3 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>, /* D10 */
		   <&gpio0 20 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&spi3_default>;
	pinctrl-1 = <&spi3_sleep>;
	pinctrl-names = "default", "sleep";

	gd25wb256: gd25wb256e3ir@1 {
		compatible = "jedec,spi-nor";
		status = "disabled";
		reg = <1>;
		spi-max-frequency = <8000000>;
		size = <268435456>;
		has-dpd;
		t-enter-dpd = <3000>;
		t-exit-dpd = <40000>;
		sfdp-bfp = [
			e5 20 f3 ff  ff ff ff 0f  44 eb 08 6b  08 3b 42 bb
			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
			10 d8 00 ff  44 7a c9 fe  83 67 26 62  ec 82 18 44
			7a 75 7a 75  04 c4 d5 5c  00 06 74 00  08 50 00 01
			];
		jedec-id = [c8 65 19];
	};
};

I noticed that button_1 is also using GPIO Pin 9. 

	buttons {
		compatible = "gpio-keys";
		button0: button_0 {
			gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
			label = "Push button 1";
			zephyr,code = <INPUT_KEY_0>;
		};
		button1: button_1 {
			gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
			label = "Push button 2";
			zephyr,code = <INPUT_KEY_1>;
		};

So, I also enabled the I/O expander in the Board configurator to free up GPIOs. However I am getting an SPI connection timeout when i try to run zperf sample app. 

Am I missing something for the device tree configuration on nrf9161? I have used the shield with nRF9160, and there, I have to disable the switch2_pin_routing in order to use GPIO Pin 9. 

Thanks in advance. 

  • Hello,

    Not tried the example, but in general timeout means that the spi was not able to drive the pins as expected (likely the CLK pin is the problematic one), this typically can happen if something externally is preventing the pin(s) to go logic low and high. 

    So can you try different pin(s) or connect a logic analyzer to check if there is any data as expected?

    Kenneth

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