We need to retrieve data from an FPGA to the nRF5340, process it with the network and Wi-Fi protocol stacks and then send the data to the nRF7002 for Wi-Fi transmission. We need very high data rates, and SPI would not be fast enough. So we would like QSPI to both the FPGA and nRF7002. But of course the nRF5340 only has one QSPI port. We see two alternatives. Can you tell me if these are feasible?
- Use two separate sets of pins for the QSPI port and swap back and forth - This may be disallowed since the highest speeds of QSPI require the use of P0.13 to P0.18 pins. And we want to use the 48 or 96 MHz QSPI clock for the FPGA communications. However, the nRF7002 QSPI is limited to 32 MHz, and the P0.08-P0.12 pins support SPIM4 running at 32 MHz, so I'm wondering if those or other pins could be used for an alternate QSPI port running at 24 or 32 MHz.
- Connect the QSPI only to the FPGA, but use a control line to route the QSPI signals to the internal QSPI slave of the FPGA, or back out to the nRF7002. - The FPGA would be acting as a very high speed MUX. Since the slower 24 or 32 MHz clock would be required for the nRF7002, the timing requirements would be eased. Writes should be no problem since the clock and data lines would all be delayed by about the same small amount. And for reads, the extra round trip time from a clock edge to the return read data would probably be ok, but there is also the IFTIMING register which allows fine tuning of when the QSPI samples the read data.
This is both a hardware and software question. I believe the second option is pretty viable from a hardware perspective. But my biggest question is whether the network stack can deal with the nRF7002 being offline for short periods of time when the QSPI needs to talk to the FPGA. Does the application have any control over when the network stack accesses the nRF7002? And if the network stack is controlling the access directly, is that library code with source that I could possibly modify? Or is it compiled binary like the BLE SoftDevice that can't be examined or touched?
The application only needs to do this for short periods, rapidly reading many megabytes of data from the FPGA and sending it out through Wi-Fi using UDP. So it would be sequential: read the data from the FPGA, process it in the MCU, then send out to the nRF7002. But I don't fully understand how the network stack interacts with the nRF7002. Once the chip is configured and the Wi-Fi connection is established, does the stack only talk to the nRF7002 when it gets an interrupt from it, or the application initiates a Wi-Fi action? Or does the network stack sometimes poll the nRF7002. If the stack only talks to the nRF7002 when the application says to or when it sees an interrupt, then I can mask the HOST_IRQ line with the FPGA when the nRF7002 is disconnected from the QSPI, and make sure the application doesn't initiate any Wi-Fi actions too during the very short time when the QSPI bus is switched to the FPGA registers instead.
I am just starting to build some tests and demo code on the nRF7002, so I don't have a full understanding of how the Wi-Fi chip and MCU communicate yet. But it is critical for our project that we get the data throughput speeds that seem to only be possible if we can use QSPI to both retrieve the data from the FPGA and then also to send it out via QSPI to the nRF7002. I really appreciate any insight you can give into whether this is possible.
