The GPIOTE peripheral in itself should fire the interrupt utmost in one HFCLK cycle.
The Cortex-M4 that is inside the nrf52840 have a maximum latency of 12 HFCLK cycles from the moment it detects the interrupt to the time it runs the ISR in the interrupt vector table.
If you are using softdevice which also have the MBR, there are additional layers of interrupt forwarding which can take upto 2-4us additional latency to forward a particular interrupt to the handler set in application vector table.
The GPIOTE peripheral in itself should fire the interrupt utmost in one HFCLK cycle.
The Cortex-M4 that is inside the nrf52840 have a maximum latency of 12 HFCLK cycles from the moment it detects the interrupt to the time it runs the ISR in the interrupt vector table.
If you are using softdevice which also have the MBR, there are additional layers of interrupt forwarding which can take upto 2-4us additional latency to forward a particular interrupt to the handler set in application vector table.
