Maximum PDM clock frequency supported by nRF5340

[Ankit Mallick]

Hi,

We wanted to implement nRF5340 with our ultrasonic microphone SPH0641LU4H-1 (https://www.knowles.com/docs/default-source/model-downloads/sph0641lu4h-1-revb.pdf?Status=Master&sfvrsn=bdc077b1_4) to sample 80kHz data. To understand the capabilities, can you support us with -

1. Can we achieve PDM clock frequency of 4.8 MHz to run the sensor in ultrasonic mode?

2. Can we sample 80kHz data at a ratio of 64? If not, what is the maximum sampling rate we can achieve?

3. How much RAM and flash will be acquired to store 80 kHz data for 1 second?

Thanks & BR,

Ankit M

[Susheel Nuguru]

Hi Ankit,

1. The nRF5340 supports Pulse Density Modulation (PDM) and can generate the PDM clock. However, based on the information provided in the nRF5340 Product Specification and nRFx PDM HAL, the maximum PDM clock frequency supported is 1.333 MHz. Therefore, achieving a PDM clock frequency of 4.8 MHz as required by your ultrasonic microphone may not be possible with the nRF5340.
2. The nRF5340 supports a selectable ratio of 64 or 80 between PDM_CLK and output sample rate as per the PDM Product Specification. However, given the maximum PDM clock frequency of 1.333 MHz, the maximum achievable sampling rate would be approximately 20.8 kHz (1.333 MHz / 64) which is less than the 80 kHz you require.
3. The amount of RAM and flash required to store 80 kHz data for 1 second would depend on the bit depth of the data. For example, if each sample is 16 bits (2 bytes), you would need approximately 160 KB of memory (80,000 samples/second * 2 bytes/sample) to store 1 second of data.

[Ankit Mallick]

Thank you for the quick response!

1. As shown in spec sheet, 1.333 MHz is highest but is this from 32MHz peripheral clock or Audio PLL clock?

2. As per the driver provided by Nordic, 1.333 MHz can be set as maximum. Can we configure the driver to achieve the 4.8 MHz frequency as the equation of PDMCLKCTRL can provide the register value needed to operate at the desired frequency?

3. Can you provide the updated library to change the PDM clock frequency to 4.8 MHz if the driver can be updated?

Thanks,

Ankit

[Susheel Nuguru]

The ratio register can only take values 64 or 80, so only very limited amount of PDM clock frequencies are achievable here. By the understanding of the documentation, changing the driver does not change the hardware limitation of getting a maximum of 1.333MHz of PDM clock.