GPIO Pin States In Pin Reset

[csheaupdesigns]

In the nrf5340 Product Specification, the GPIO registers OUT, DIR, LATCH, DETECTMODE, DETECTMODE_SEC, and PIN_CNF[n] are all labeled as "Retained Registers".  The definition of a retained register according to section 4.10.8 is the following:

"A retained register is one that retains its value in System OFF and/or Force-OFF modes and when reset, depending on the reset source. See individual peripheral chapters for information about which registers are retained for the various peripherals."

Table 9 in section 4.10.9 displays the reset behavior of the GPIO retained registers for all possible Reset Sources.  Looking at the table below, a Pin Reset should result in the GPIO retained registers reverting to their reset values.  Empirically, I am experiencing behavior different than that described by Table 9.  If I hold the nrf5340 in the pin reset state, I'm noticing that the pin states stay at the values that they were last set to when the pin reset first occurred.  This would imply that the GPIO retained registers are retaining their values while in the reset state.

Can someone provide some clarity on what behavior I should expect in the pin reset state?  Am I interpreting the Product Specification incorrectly?

[Kenneth]

Hello,

Think the confusion here may come from what happens upon release of reset, so when pin reset is de-asserted the program will run from start of program execution, and the gpio peripheral is then reset, it's not necessarily the case that the pins will be reset when reset pin is asserted. While the pin reset is asserted it's likely a bit undefined what the behavior is, e.g. depending on the pins are controlled by a serial peripheral (e.g. spi, uart etc) or directly by the gpio peripheral. It's not intended to keep the pin reset asserted for a long period of time, since the current consumption can also be up to active current during this period.

Kenneth