Pin reset on nRF52805 and use of internal pullup

[EngineerB]

1) On p. 55 of nRF52805_PS_v1.4.pdf, section "5.3.8 Reset behavior" shows that a pin reset will reset GPIO, so will a pin reset active low also reset PSELRESET registers, so that the pin is no longer programmed as reset? If so, then holding pin reset low cannot hold the device in reset? (because as soon as it goes low the pin reset is unprogrammed) UNLESS the device does not reset until the pin reset goes inactive (high) after having been low – is that what happens to prevent the pin reset from being deprogrammed when pin reset goes low?

 

2) When pin reset is programmed onto P0.21 using the PSELRESET registers, does this also program an internal pullup resistor on that pin, or would that need to be programmed separately? If programmed to use the internal 13K pullup (on P0.21), will that persist while pin reset is held low, or will the internal pin reset pullup be disconnected as soon as the pin reset goes low, leaving it floating low?

 

3) Do we need to poll the state of the pin reset GPIO pin before configuring it as pin reset using the PSELRESET register, and if it is still low, wait for it to be pulled high before enabling pin reset in the PSELRESET register? We are planning to have a capacitor to ground across pin reset which will cause some delay in it reaching a high logic level upon power-up.

[Simonr]

Hi

So after discussing with a colleague, the UICR and FICR register are used to change the default reset value for peripherals, so the reset value for P0.21 will be changed so that it never is set as a GPIO. Why are you asking exactly? What's the use case you're looking to implement this for?

When pin reset is programmed onto P0.21 using the PSELRESET registers, does this also program an internal pullup resistor on that pin

Yes, it will also program an internal pullup on that pin.

Best regards,

Simon

[EngineerB]

Apparently PSELREST[n] are UICR registers which means they are non-volatile. What confused me was that in the Product Specification document it was shown to be set to all 1's by Reset. However, is that "Reset" a flash erase function in this case rather than a device reset due to power-up or pin reset? If so, then I believe what you are saying is that once programmed, unless specifically erased in NVM, the PSELREST[n] registers remain programmed to the reset function even after a pin reset or power-up reset, is that correct?

In our case we would like to drive the reset pin with open-drain (aka open-collector) drivers, so that multiple sources could pull the pin low without conflict. We also have a small capacitor from pin reset to ground to filter out noise. Thus we require a pull-up resistor to pull the pin high. If the internal pull-up resistor is automatically enabled when pin reset is enabled in the PSELREST[n] registers, then the next time the device goes through power-up reset . the capacitor will be charged by the internal pull-up resistor, and the rate of charging of the capacitor will delay emergence from reset until that capacitor charges to a logic 1 on the pin reset pin, is that correct?