1) On p. 55 of nRF52805_PS_v1.4.pdf, section "5.3.8 Reset behavior" shows that a pin reset will reset GPIO, so will a pin reset active low also reset PSELRESET registers, so that the pin is no longer programmed as reset? If so, then holding pin reset low cannot hold the device in reset? (because as soon as it goes low the pin reset is unprogrammed) UNLESS the device does not reset until the pin reset goes inactive (high) after having been low – is that what happens to prevent the pin reset from being deprogrammed when pin reset goes low?
2) When pin reset is programmed onto P0.21 using the PSELRESET registers, does this also program an internal pullup resistor on that pin, or would that need to be programmed separately? If programmed to use the internal 13K pullup (on P0.21), will that persist while pin reset is held low, or will the internal pin reset pullup be disconnected as soon as the pin reset goes low, leaving it floating low?
3) Do we need to poll the state of the pin reset GPIO pin before configuring it as pin reset using the PSELRESET register, and if it is still low, wait for it to be pulled high before enabling pin reset in the PSELRESET register? We are planning to have a capacitor to ground across pin reset which will cause some delay in it reaching a high logic level upon power-up.
