Cannot build I2S echo application for NRF5340

Hi, I am a beginner into the embedded audio space, and happened upon this board to use for our university project. Our team's current plan would be to produce audio directly on the board and play it through the headphone jack, but have not found much success with the NRF5340 Audio application, as it has a lot of integration with Bluetooth (which we don't need for now). Right now we just need a simple application that plays a tune on the board.

In my search I have found the I2S echo application, which seems like a simple start for our use case. However, when trying to build the application we encountered the following error:

-- Found BOARD.dts: C:/ncs/v2.6.2/zephyr/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts
-- Found devicetree overlay: boards/nrf5340dk_nrf5340_cpuapp.overlay
devicetree error: pinctrl-names property in /soc/peripheral@50000000/i2s@28000 in C:/ncs/v2.6.2/zephyr/misc/empty_file.c has 1 strings, expected 2 strings

This is our build configuration (all other options left as default):

SDK version:

Any help would be appreciated! Thanks!

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  • This is literally the absolute pinnacle of my current knowledge at the moment. I haven't tried any other sample rates or bit depths, nor do I even know how to play anything longer than will fit in the I2S buffer, which is limited to about 1 second at 48kHz. Memslabs and continuous arrays are still on my reading list.

    My learning curve to this point has been painfully steep. Nordic's documentation seems to assume that programmers only need a syntax reference rather than any informative explanation, so my actual understanding of the details thus far is tentative at best.

    The LRCLK (Left Right clock) or WSCLK (Word Select clock) toggles high and low for each audio channel's transmission, and is indeed equivalent to the sample rate. I'm using the undivided (bypassed) nRF53 ACLK as the source to FLL1 via the MCLK1 input, which dictates all the other clock and sampling rates in the system. You'll likely have to divide ACLK (aka MCLK1) via the I2S registers, and then compensate by changing FLL1's configuration.

    Section 4.10 Clocking and Sample Rates in the CS47L63 datasheet has plenty of further details to study, and the cs47l63_fll_*() functions defined in cs47l63.h are invaluable for configuring the complicated FLLs.

    That should get you started, and I'm happy to hear you learned a little something from my effort.

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