In Section 6.17.1, page 543, of the nRF52840 product specification version 1.10, in regard to the Pulse-Width Modulation (PWM) peripheral, there is a statement that says
> The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n]
is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to
FallingEdge.
There are two aspects of this statement that are incorrect (at least for the AAD0 variant on the board I'm using):
- First, if the compare value is not reached (because it is larger than the COUNTERTOP value), there will be no transition, and the OUT[n] will never change throughout the period. Therefore, when the COUNTERTOP value is reached and the counter is reset, the signal will not invert. In this case, it will remain the same.
- Second, setting a compare value of 0 with a FallingEdge polarity does not hold OUT[n] to a low value. Instead, there is a brief glitch in the OUT[n] signal where the signal very briefly goes high, then falls low. This creates a "spike" in the output signal, which some devices will notice and react to. The only reliable way to get the PWM module to produce a pure low signal on OUT[n] is to specify a RisingEdge polarity with a compare value that is strictly larger than the COUNTERTOP value.
Both of these have been verified using an oscilloscope.