Oscillator Drift caused by beneath GND layer

[MarkusF]

Hello everyone,

we are currently designing a PCB based on the nRF52840. The system is dependent on high accurracy of HFXO.

In an old blog post on the TI forum I found a discussion suggesting the following: A GND layer directly beneath high freq clock source is not recommended as it can slow down the oscillator by parasitic capacitace.

https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/116088/what-causes-big-clock-drift

The dev boards (nrf52840) seem to have a GND layer directely beneath both external oscillators.

As BLE is also dependent on the accurracy of clock sources, I was wondering if you could share some insights  / recommendations on this topic?

Thanks!

Markus

[mathiaso]

Hi, Markus.

It is possible that the distance between the crystal and the ground layer below might have an impact on the applied load capacitance. However, the value of the capacitors connected to the crystal connections should have a greater effect. In general, we recommend following the reference/DK design. You can see in those designs that no data traces are running right next to the crystal and its traces nor any traces directly below.

Regarding the value of the crystal capacitors, the recommendation is to use capacitors with a value Ccap = 2 * CL - (Cpin + Cpcb), where CL is the crystal's load capacitance and 4 pF is usually a good approximation for (Cpin + Cpcb), as explained in this guide.

To check if your device is within the HFXO tolerance requirements, you can, e.g., use the Radio test (short-range) sample and measure the deviation from the selected channel frequency.

Best regards,
Mathias