Regarding the I2C (TWI) clock in nRF5340.

[sst_S.Sakamoto]

Hello,

I am using the following device and development kit:

• Device: NORA-B106-00B (nRF5340)
• nRF Connect SDK: 2.0.2

Currently, to ensure that the connected device receives the correct result of the command in an I2C operation, it requires a 66μs wait time between issuing the command and reading the result.

If you set the I2C (TWI) clock frequency to the standard 100kHz (10μs), the clock (SCL) when reading the results from the device may have a spike shape as shown in the figure below.

This may cause I2C communication to fail.

If you set the clock frequency to 10kHz (100μs), as shown in the figure below, the clock (SCL) does not change significantly when reading the results from the device, and I2C communication seems to be occurring normally.

(The method for setting the clock frequency to 10kHz is based on How can I set a non-standard speed for the I2C bus using the Zephyr? - Nordic Q&A - Nordic DevZone)

There are some points that I would like to confirm based on the above points.

1. Is it acceptable for the clock (SCL) to be shortened due to the influence of the device?
2. In the nRF5340 specifications, there are only 4 patterns for the TWI clock frequency (100kHz, 250kHz, 400kHz, 1MHz), but is there any problem with using 10kHz?

Best regards,

[Simonr]

Hi

I think the i2c_write() from the Zephyr API is the way to go here. Adding a wait function should be fine AFAIK, what exactly are you having trouble with? We have some TWIM/TWIS samples available here that should be usable: https://github.com/zephyrproject-rtos/hal_nordic/tree/master/nrfx/samples/src/nrfx_twim_twis 

Best regards,

Simon

[sst_S.Sakamoto]

Hello Simon,

Thank you for providing the sample.

I think the problem is that after the slave receives data via I2C and performs clock stretching (66 μs), the first clock pulse from the master becomes longer or shorter, which can cause an error when the slave responds.

This is also described in the errata document at the URL below.

https://docs.nordicsemi.com/bundle/errata_nRF5340_EngA/page/ERR/nRF5340/EngineeringA/latest/anomaly_340_37.html#anomaly_340_37

Therefore, by setting a wait time between when the master sends data and when the slave responds, I hope that a normal clock pulse will be generated from the master when the slave responds.

Is the above thinking correct?

Best regards,