Hi, we are seeing an rare issue that might be connected to PAN #57 for NRF51822 and are looking for some more info on this.
I assume the underlying issue is some form of read-modify-write race condition
for example lets say i configure group #0 to contain PPI channel #0
* If 2 PPIs are triggering group disable for group #0 on same clock cycle, can that fail, since the two writes will try to make the same change?
* If 1 PPI is triggering group disable for group #0 and code is trying to enable PPI channel #1, is there anything you can tell me of what will happen, will only PPI #0 and #1 be affected or could some other channel, #2 get changed?
