TWI Master/Slave frequency and delay

[remtec]

Hi. I tried using the TWI master and slave drivers on 2 different nRF52840DK boards.
The 100KHz frequency is perhaps a little high and I will see how to lower it by acting on the FREQUENCY reg to have more squared signals.

However, I was unable to reduce the pause time between the first byte of address + ACK and the start of receiving the 8 bytes read from the master.

What is the cause of this useless delay of over 1 msec?
Can it be reduced?

[remtec]

HI. The sample I used sets interrupt for the twis, but does not use interrupt for the twim: could this be what causes that delay in handling the read?
Probably due to rtos! Is this correct?
I'm using nrf connect sdk 2.3.0.

[remtec]

Ok. I created a customized I2C Master driver to verify the TWIS response: during writing, the ACK is recognized, and it listens to the first byte, but then blocks SCL for 2-3 msec and does not allow continuing.
Has anyone encountered this behavior before?