How to limit QSPI to 48 MHz on the nRF7002DK / nRF5340?

[Saxman58]

The nRF7002DK board has a Vdd of 1.8 V, unlike every other Nordic board I've seen which use 3.3V.  I assume this is due to the nRF5340 errata that state that the QSPI bus (used to connect to the nRF7002) doesn't function properly at 96 MHz for Vdd > 2.0 V.  Another errata states that the radio performance (both BT and Wi-Fi?) is significantly degraded with 96 MHZ QSPI at a higher voltage.  See:

https://docs.nordicsemi.com/bundle/errata_nRF5340_Rev1/page/ERR/nRF5340/Rev1/latest/anomaly_340_136.html#anomaly_340_136

and

https://docs.nordicsemi.com/bundle/errata_nRF5340_Rev1/page/ERR/nRF5340/Rev1/latest/anomaly_340_133.html

How can I set the QSPI clock high frequency with the nRF Connect SDK?  I see that the device tree sets sck-frequency = 24 MHz, but it looks like the driver code boosts that during some operations (to 96 MHz I believe - I don't have a fast scope handy).  Is there a user setting that will affect the boosted frequency, or is that buried in the driver code?

Wi-Fi throughput is critical to us, so I would like to see how our application is affected by using 48 MHz instead of 96 MHz for the QSPI.  If the system throughput is not affected much, it might be better for us to run at 48 MHz to allow the use of 3.3V serial ports.

[Håkon Alseth]

Hi,

 

There are two different clocks, one that goes into the QSPI (PCLK), and the actual QSPI output.

The PCLK, controlled in CLOCK domain, is 192 MHz, which can be divided by 1, 2, or 4, providing 192/96/48 MHz options.

 

Switching the PCLK to 48 MHz is a requirement in order to obtain a low current consumption in sleep, as explained here:

https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/clock/doc/clock.html#ariaid-title3

 

In addition to #133 and #136, there is this erratum #159: https://docs.nordicsemi.com/bundle/errata_nRF5340_Rev1/page/ERR/nRF5340/Rev1/latest/anomaly_340_159.html

 

I assume this is due to the nRF5340 errata that state that the QSPI bus (used to connect to the nRF7002) doesn't function properly at 96 MHz for Vdd > 2.0 V.  Another errata states that the radio performance (both BT and Wi-Fi?) is significantly degraded with 96 MHZ QSPI at a higher voltage.  See:

This is related to the nRF5340 radio performance.

How can I set the QSPI clock high frequency with the nRF Connect SDK?  I see that the device tree sets sck-frequency = 24 MHz, but it looks like the driver code boosts that during some operations (to 96 MHz I believe - I don't have a fast scope handy).  Is there a user setting that will affect the boosted frequency, or is that buried in the driver code?

The QSPI output speed is set in device tree.

The qspi driver in NCS will handle "active" and "inactive" (ie. for low power mode), as per the above linked errata #159. This means that when the QSPI is active, it will run on PCLK != 48 MHz.

Wi-Fi throughput is critical to us, so I would like to see how our application is affected by using 48 MHz instead of 96 MHz for the QSPI.  If the system throughput is not affected much, it might be better for us to run at 48 MHz to allow the use of 3.3V serial ports.

The QSPI output speed is limited by the nRF7002 in this case. Due to the different erratas related to the QSPI, we strongly recommend to use < 2.0V IO voltage.

If you need 3.3V operation, SPI operation can be used, but this will lower the overall throughput.

 

Kind regards,

Håkon