nRF54L15 - NFCT Pins as GPIO with TF-M

[MarkLaloo]

Good day,

I'm trying to use pin 1.02 as a GPIO in a TF-M build using a (custom) non-secure board target, and I'm struggling to find the appropriate way to accomplish this. 

All current resources point to deprecated Kconfig defines (USE_NFCT_PINS_AS_GPIO), do not support non-secure targets (uisng the &uicr node in devicetree), are for older SoCs (

TFM_NFCT_PINS_AS_GPIOS only applies to nRF5340 according to v2.9.0 SDK). The only working option I've found is to edit the NFCT PADCONFIG register (which worked); are there any other options?

Thank you

Kind regards,

Mark Laloo

[Hieu]

Hi Mark,

Referring to this earlier DevZone case:  nRF5340: best way to configure P0.02 (NFCT) as GPIO with TFM .

As long as the NFC node is disabled in DeviceTree on the non-secure target, P1.02 will be enabled as a GPIO pin by default.

Best regards,

Hieu

[MarkLaloo]

HI Hieu,

Thanks for the response. I've seen this post before, with no luck. 

I've tried disabled the NFC node using:

&nfct {

    status = "disabled";

};

in board_nrf54l15_cpuapp_ns.dts, and after testing again, this does not solve the issue. Debugging in VSCode/Ozone and inspecting the registers, PADCONFIG is still enabled in the NFCT_NS register, and the pin does not function as a GPIO unless I manually disable. Worth noting, the TFM_NFCT_PINS_AS_GPIO appears to target only the 5340 SoC. Is there perhaps something I'm missing alongside the NFCT node change in devicetree?

Kind regards,
Mark Laloo 

[Hieu]

Hi Mark,

My apology. I am able to reproduce the issue. I actually am not able to work around it by writing to NRF_NFCT_NS->PADCONFIG. Did you write to that register from the secure domain?

I am also asking internally if there is any DeviceTree method for this instead. I will get back to you when I got an answer.

Best regards,

Hieu

[Hieu]

Hi Mark,

Unfortunately, the people working on the DeviceTree solution are unavailable at the moment.

I also would like to correct that writing NRF_NFCT_NS->PADCONFIG works. I didn't know that P1.02 isn't connected from the SoC to the pin header on the DK. Checking R33 on the DK shows that the pin works normally.

Could you please use the direct register write method for now?

I will file an internal ticket for a driver approach solution to the problem.

Best regards,

Hieu

[MarkLaloo]

HI Hieu,

Thank you for the response; we will continue using the PADCONFIG register until a driver solution is available.

Kind regards,
Mark Laloo