SENT protocol based sensor configuration with nrf boards

hey there, i have a project which uses  nrf9151 with a pressures sensor from BOSCH which uses SENT protocol to transfer data, my question is

1. Is it possible to configure the SENT protocol on the nrf9151
2. if yes, how am i gonna configure what should i use?

Parents
  • The above is my implementation according to this

    SENT protocol driver using nRF Timer captures

    can someone please guide me where am i going wrong because i am unable to read any capture falling to falling edge period.

    thank you

  • I thought of an improved algorithm which uses no cpu time or interrupts until the entire SENT message has been captured in Timer registers. Two counters and two Timers are required, since there are 10 edges and capture events, and data is captured as distinct messages, which is of course how they are sent in practice. The message can actually be read out while the optional Pause field is being transmitted, and there is more time until the next message starts.

    Timer/Counters 0, 1 & 2 have 4 CC registers each; Timer/Counters 3 & 4 have 6 CC registers each:
     - COUNTER3 counts 1st 6 edges: set CC0=1, CC1=2, CC2=3, CC3=4, CC4=5, CC5=6
     - COUNTER2 counts next 4 edges: set CC0=7, CC1=8, CC2=9, CC3=10
     - TIMER4 saves the elapsed message time at the first 6 edges
     - TIMER1 saves the elapsed message time at the next 4 edges

    Both of these counters use PPI to count the negative-going edges

    // SENT protocol
    // SENT tick ranges from 3us to about 90us, with clock-rate tolerances as high as +-25%. Each
    // nibble begins with a 5us logic low followed by a variable-width logic-high pulse
    //
    // A SENT message frame includes a sync signal followed by eight nibbles and an optional pause,
    // the latter  to make up fixed-length messages
    // A nibble ranges from 12 to 27 ticks (representing 0x0 to 0xF), optional Pause is 12-768 ticks
    //
    //             |--------Fast Channel Data--------|       Optional
    // Sync  Stat    DN1   DN2   DN3   DN4   DN5   DN6   CRC    PAUSE
    // ====  ===== ===== ===== ===== ===== ===== ===== ===== ========
    // T4[0] T4[1] T4[2] T4[3] T4[4] T4[5] T1[0] T1[1] T1[2]    T1[3]  <== Timer Capture CC register Id
    //     ^     ^     ^     ^     ^     ^     ^     ^     ^        ^
    //     |     |     |     |     |     |     |     |     |        |  <== Counter compare triggers Timer capture
    //     |     |     |     |     |     |     |     |     |        |
    // C3[0] C3[1] C3[2] C3[3] C3[4] C3[5] C2[0] C2[1] C2[2]    C2[3]  <== Counter Compare CC register Id
    //     ^     ^     ^     ^     ^     ^     ^     ^     ^        ^
    //     |     |     |     |     |     |     |     |     |        |  <== Falling edge triggers counter increment
    //     |     |     |     |     |     |     |     |     |        |
    // ----+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+    +---+
    //     | ||||| ||||| ||||| ||||| ||||| ||||| ||||| |||||    |||||  <== Nibble Framing
    //     +-+   +-+   +-+   +-+   +-+   +-+   +-+   +-+   +----+   +-
    //     |     |     |     |     |     |     |     |     |        |
    //  56   12-27 12-27 12-27 12-27 12-27 12-27 12-27 12-27 (12-768)  <== SENT numer of Ticks range
    //   0       1     2     3     4     5     6     7     8      (9)  <== SENT Falling Edge Number
    // ====  ===== ===== ===== ===== ===== ===== ===== ===== ========
    // Sync  Stat    DN1   DN2   DN3   DN4   DN5   DN6   CRC    PAUSE
    //             |--------Fast Channel Data--------|       Optional

    This is the algorithm:

    //  COUNTER3 counts 1st 6 edges:  set CC0=1, CC1=2, CC2=3, CC3=4, CC4=5, CC5=6
    //  COUNTER2 counts next 4 edges: set CC0=7, CC1=8, CC2=9, CC3=10
    //  TIMER1 saves the elapsed message time at the next 4 edges
    //  START TIMER4 and TIMER5 together (use PPI event)
    //  START TIMER4 and TIMER5 together (use PPI event)
    //  START COUNTER3 and COUNTER2 together (use PPI event)
    //  Single Message
    //  {
    //    Counter EVENT      Timer Mode TASK     Nibble  Read registers
    //    =============      =================   ======  =================================
    //    Counter3-CC0  ==> capture Timer4-CC0   Sync
    //    Counter3-CC1  ==> capture Timer4-CC1   Status
    //    Counter3-CC2  ==> capture Timer4-CC2   DN1
    //    Counter3-CC3  ==> capture Timer4-CC3   DN2
    //    Counter3-CC4  ==> capture Timer4-CC4   DN3
    //    Counter3-CC5  ==> capture Timer4-CC5   DN4
    //    Counter2-CC0  ==> capture Timer1-CC0   DN5
    //    Counter2-CC1  ==> capture Timer1-CC1   DN6
    //    Counter2-CC2  ==> capture Timer1-CC2   CRC    Can start reading in interrupt here
    //    Counter2-CC3  ==> capture Timer1-CC3   PAUSE  read Timer4 CC0-CC5 and Timer1 CC0-CC3
    //  }

Reply
  • I thought of an improved algorithm which uses no cpu time or interrupts until the entire SENT message has been captured in Timer registers. Two counters and two Timers are required, since there are 10 edges and capture events, and data is captured as distinct messages, which is of course how they are sent in practice. The message can actually be read out while the optional Pause field is being transmitted, and there is more time until the next message starts.

    Timer/Counters 0, 1 & 2 have 4 CC registers each; Timer/Counters 3 & 4 have 6 CC registers each:
     - COUNTER3 counts 1st 6 edges: set CC0=1, CC1=2, CC2=3, CC3=4, CC4=5, CC5=6
     - COUNTER2 counts next 4 edges: set CC0=7, CC1=8, CC2=9, CC3=10
     - TIMER4 saves the elapsed message time at the first 6 edges
     - TIMER1 saves the elapsed message time at the next 4 edges

    Both of these counters use PPI to count the negative-going edges

    // SENT protocol
    // SENT tick ranges from 3us to about 90us, with clock-rate tolerances as high as +-25%. Each
    // nibble begins with a 5us logic low followed by a variable-width logic-high pulse
    //
    // A SENT message frame includes a sync signal followed by eight nibbles and an optional pause,
    // the latter  to make up fixed-length messages
    // A nibble ranges from 12 to 27 ticks (representing 0x0 to 0xF), optional Pause is 12-768 ticks
    //
    //             |--------Fast Channel Data--------|       Optional
    // Sync  Stat    DN1   DN2   DN3   DN4   DN5   DN6   CRC    PAUSE
    // ====  ===== ===== ===== ===== ===== ===== ===== ===== ========
    // T4[0] T4[1] T4[2] T4[3] T4[4] T4[5] T1[0] T1[1] T1[2]    T1[3]  <== Timer Capture CC register Id
    //     ^     ^     ^     ^     ^     ^     ^     ^     ^        ^
    //     |     |     |     |     |     |     |     |     |        |  <== Counter compare triggers Timer capture
    //     |     |     |     |     |     |     |     |     |        |
    // C3[0] C3[1] C3[2] C3[3] C3[4] C3[5] C2[0] C2[1] C2[2]    C2[3]  <== Counter Compare CC register Id
    //     ^     ^     ^     ^     ^     ^     ^     ^     ^        ^
    //     |     |     |     |     |     |     |     |     |        |  <== Falling edge triggers counter increment
    //     |     |     |     |     |     |     |     |     |        |
    // ----+ +---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+    +---+
    //     | ||||| ||||| ||||| ||||| ||||| ||||| ||||| |||||    |||||  <== Nibble Framing
    //     +-+   +-+   +-+   +-+   +-+   +-+   +-+   +-+   +----+   +-
    //     |     |     |     |     |     |     |     |     |        |
    //  56   12-27 12-27 12-27 12-27 12-27 12-27 12-27 12-27 (12-768)  <== SENT numer of Ticks range
    //   0       1     2     3     4     5     6     7     8      (9)  <== SENT Falling Edge Number
    // ====  ===== ===== ===== ===== ===== ===== ===== ===== ========
    // Sync  Stat    DN1   DN2   DN3   DN4   DN5   DN6   CRC    PAUSE
    //             |--------Fast Channel Data--------|       Optional

    This is the algorithm:

    //  COUNTER3 counts 1st 6 edges:  set CC0=1, CC1=2, CC2=3, CC3=4, CC4=5, CC5=6
    //  COUNTER2 counts next 4 edges: set CC0=7, CC1=8, CC2=9, CC3=10
    //  TIMER1 saves the elapsed message time at the next 4 edges
    //  START TIMER4 and TIMER5 together (use PPI event)
    //  START TIMER4 and TIMER5 together (use PPI event)
    //  START COUNTER3 and COUNTER2 together (use PPI event)
    //  Single Message
    //  {
    //    Counter EVENT      Timer Mode TASK     Nibble  Read registers
    //    =============      =================   ======  =================================
    //    Counter3-CC0  ==> capture Timer4-CC0   Sync
    //    Counter3-CC1  ==> capture Timer4-CC1   Status
    //    Counter3-CC2  ==> capture Timer4-CC2   DN1
    //    Counter3-CC3  ==> capture Timer4-CC3   DN2
    //    Counter3-CC4  ==> capture Timer4-CC4   DN3
    //    Counter3-CC5  ==> capture Timer4-CC5   DN4
    //    Counter2-CC0  ==> capture Timer1-CC0   DN5
    //    Counter2-CC1  ==> capture Timer1-CC1   DN6
    //    Counter2-CC2  ==> capture Timer1-CC2   CRC    Can start reading in interrupt here
    //    Counter2-CC3  ==> capture Timer1-CC3   PAUSE  read Timer4 CC0-CC5 and Timer1 CC0-CC3
    //  }

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