The address miss event is not shown as a transition in Figure 22 of the NRF51 Reference Manual. What state does the NRF51 enter upon an address miss and how long after the address miss does it take to enter this state?
The address miss event is not shown as a transition in Figure 22 of the NRF51 Reference Manual. What state does the NRF51 enter upon an address miss and how long after the address miss does it take to enter this state?
Please reference chapter 17.1.13 Device address match to see how the address match feature works. Note that it's possible to enable interrupt on both match and miss in INTENSET -> DEVMATCH and DEVMISS.